default_vendor_com addon ARM IP registers. Address map for the HHP HPS system-domain dmanonsecure Address space allocated to the nonsecure DMA. For detailed information about the use of this address space, [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html]click here[/url] to access the ARM documentation for the DMA-330. DSR 3.3.1. DMA Manager Status Register The DSR Register characteristics are: Purpose Returns information about the status of the DMA manager thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO DNS Provides the security status of the DMA manager thread: 0 = DMA manager operates in the Secure state 1 = DMA manager operates in the Non-secure state. Note You must use the boot_manager_ns signal to set the secure state of the DMA manager thread. Wakeup_event When the DMA manager thread executes a DMAWFE instruction, it waits for the following event to occur: b00000 = event[0] b00001 = event[1] b00010 = event[2] . . . b11111 = event[31]. DMA_status The operating state of the DMA manager: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101-b1110 = reserved b1111 = Faulting. DPC 3.3.2. DMA Program Counter Register The DPC Register characteristics are: Purpose Provides the value of the program counter for the DMA manager thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_mgr Program counter for the DMA manager thread INTEN 3.3.3. Interrupt Enable Register The INTEN Register characteristics are: Purpose When the DMAC executes a DMASEV instruction, each bit of the INTEN Register controls if the DMAC signals: The specified event to all of the threads. An interrupt using the corresponding irq. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RW / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RW event_irq_select Program the appropriate bit to control how the DMAC responds when it executes DMASEV: Bit [N] = 0 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC signals event N to all of the threads. Set bit [N] to 0 if your system design does not use irq[N] to signal an interrupt request. Bit [N] = 1 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC sets irq[N] HIGH. Set bit [N] to 1 if your system design requires irq[N] to signal an interrupt request. Note See DMASEV for information about selecting an event number. MSB is event_irq_select for event 31 LSB is event_irq_select for event 0 INT_EVENT_RIS 3.3.4. Event-Interrupt Raw Status Register The INT_EVENT_RIS Register characteristics are: Purpose Returns the status of the event-interrupt resources. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO DMASEV_active Returns the status of the event-interrupt resources: Bit [N] = 0 Event N is inactive or irq[N] is LOW. Bit [N] = 1 Event N is active or irq[N] is HIGH. Note When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register controls whether the DMAC: * Signals an interrupt using the appropriate irq. * Sends the event to all of the threads. Note The DMAC clears bit [N] when either: * The INTEN Register is programmed to process the event and the DMAC executes a DMAWFE instruction for that event. * The INTEN Register is programmed to signal an interrupt and you write to the corresponding bit in the INTCLR Register, see Interrupt Clear Register. MSB is DMASEV [31] active LSB is DMASEV [0] active INTMIS 3.3.5. Interrupt Status Register The INTMIS Register characteristics are: Purpose Provides the status of the active interrupts in the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO irq_status Provides the status of the interrupts that are active in the DMAC: Bit [N] = 0 Interrupt N is inactive and therefore irq[N] is LOW. Bit [N] = 1 Interrupt N is active and therefore irq[N] is HIGH. Note You must use the INTCLR Register to set bit [N] to 0, see Interrupt Clear Register. Note Bit [N] is 0 if the INTEN Register programs DMASEV to signal an event, see Interrupt Enable Register. MSB is irq_status for irq[31] LSB is irq_status for irq[0] INTCLR 3.3.6. Interrupt Clear Register The INTCLR Register characteristics are: Purpose Provides the status of the active interrupts in the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO irq_clr Controls the clearing of the irq outputs: Bit [N] = 0 The status of irq[N] does not change. Bit [N] = 1 The DMAC sets irq[N] LOW if the INTEN Register programs the DMAC to signal an interrupt. Otherwise, the status of irq[N] does not change. See Interrupt Enable Register. MSB is irq_clr for irq[31] LSB is irq_clr for irq[0] FSRD 3.3.7. Fault Status DMA Manager Register The FSRD Register characteristics are: Purpose Provides the fault status of the DMA manager. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO fs_mgr Provides the fault status of the DMA manager. Read as: 0 = the DMA manager thread is not in the Faulting state 1 = the DMA manager thread is in the Faulting state. See Fault Type DMA Manager Register for information about the type of fault that occurred. FSRC 3.3.8. Fault Status DMA Channel Register The FSRC Register characteristics are: Purpose Provides the fault status for the DMA channels. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO fault_status Each bit provides the fault status of the corresponding channel. Read as: Bit [N] = 0 No fault is present on DMA channel N. Bit [N] = 1 DMA channel N is in the Faulting or Faulting completing state. See Fault Type DMA Channel Registers for information about the type of fault that occurred. MSB is fault_status for DMA channel 7 LSB is fault_status for DMA channel 0 FTRD 3.3.9. Fault Type DMA Manager Register The FTRD Register characteristics are: Purpose Provides the type of fault that occurred to move the DMA manager to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dbg_instr If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. mgr_evnt_err Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = the DMA manager has appropriate security to execute DMAWFE or DMASEV 1 = a DMA manager thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. dmago_err Indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security permissions: 0 = the DMA manager has appropriate security to execute DMAGO 1 = a DMA manager thread in the Non-secure state attempted to execute DMAGO to create a DMA channel operating in the Secure state. operand_invalid Indicates whether the DMA manager was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. undef_instr Indicates whether the DMA manager was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. FTR0 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 0) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR1 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 1) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR2 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 2) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR3 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 3) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR4 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 4) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR5 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 5) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR6 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 6) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR7 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 7) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. CSR0 3.3.11. Channel Status Registers (Channel status for DMA channel 0) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC0 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 0) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR1 3.3.11. Channel Status Registers (Channel status for DMA channel 1) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC1 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 1) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR2 3.3.11. Channel Status Registers (Channel status for DMA channel 2) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC2 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 2) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR3 3.3.11. Channel Status Registers (Channel status for DMA channel 3) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC3 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 3) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR4 3.3.11. Channel Status Registers (Channel status for DMA channel 4) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC4 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 4) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR5 3.3.11. Channel Status Registers (Channel status for DMA channel 5) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC5 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 5) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR6 3.3.11. Channel Status Registers (Channel status for DMA channel 6) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC6 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 6) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR7 3.3.11. Channel Status Registers (Channel status for DMA channel 7) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC7 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 7) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. SAR0 3.3.13. Source Address Registers (Source address for DMA channel 0) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR0 3.3.14. Destination Address Registers (Destination address for DMA channel 0) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR0 3.3.15. Channel Control Registers (Channel control for DMA channel 0) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_0 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 0) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_0 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 0) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR1 3.3.13. Source Address Registers (Source address for DMA channel 1) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR1 3.3.14. Destination Address Registers (Destination address for DMA channel 1) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR1 3.3.15. Channel Control Registers (Channel control for DMA channel 1) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_1 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 1) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_1 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 1) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR2 3.3.13. Source Address Registers (Source address for DMA channel 2) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR2 3.3.14. Destination Address Registers (Destination address for DMA channel 2) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR2 3.3.15. Channel Control Registers (Channel control for DMA channel 2) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_2 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 2) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_2 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 2) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR3 3.3.13. Source Address Registers (Source address for DMA channel 3) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR3 3.3.14. Destination Address Registers (Destination address for DMA channel 3) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR3 3.3.15. Channel Control Registers (Channel control for DMA channel 3) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_3 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 3) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_3 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 3) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR4 3.3.13. Source Address Registers (Source address for DMA channel 4) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR4 3.3.14. Destination Address Registers (Destination address for DMA channel 4) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR4 3.3.15. Channel Control Registers (Channel control for DMA channel 4) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_4 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 4) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_4 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 4) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR5 3.3.13. Source Address Registers (Source address for DMA channel 5) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR5 3.3.14. Destination Address Registers (Destination address for DMA channel 5) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR5 3.3.15. Channel Control Registers (Channel control for DMA channel 5) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_5 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 5) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_5 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 5) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR6 3.3.13. Source Address Registers (Source address for DMA channel 6) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR6 3.3.14. Destination Address Registers (Destination address for DMA channel 6) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR6 3.3.15. Channel Control Registers (Channel control for DMA channel 6) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_6 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 6) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_6 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 6) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR7 3.3.13. Source Address Registers (Source address for DMA channel 7) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR7 3.3.14. Destination Address Registers (Destination address for DMA channel 7) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR7 3.3.15. Channel Control Registers (Channel control for DMA channel 7) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_7 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 7) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_7 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 7) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations DBGSTATUS 3.3.18. Debug Status Register The DBGSTATUS Register characteristics are: Purpose Provides the debug status of the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dbgstatus The debug status encoding is: 0 = Idle 1 = Busy. DBGCMD 3.3.19. Debug Command Register The DBGCMD Register characteristics are: Purpose Controls the execution of debug commands in the DMAC as Issuing instructions to the DMAC using an APB interface describes. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO dbgcmd The debug encoding is as follows: 0b00 = execute the instruction that the DBGINST [1:0] Registers contain 0b01 = reserved 0b10 = reserved 0b11 = reserved. DBGINST0 3.3.20. Debug Instruction-0 Register The DBGINST0 Register characteristics are: Purpose Controls the debug instruction, channel, and thread information for the DMAC. See Issuing instructions to the DMAC using an APB interface for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO instruction_byte_1 instruction byte 1. instruction_byte_0 instruction byte 0. Channel_number DMA channel number: 0b000 = DMA channel 0 0b001 = DMA channel 1 0b010 = DMA channel 2 . . . 0b111 = DMA channel 7. Debug_thread The debug thread encoding is as follows: 0 = DMA manager thread 1 = DMA channel. Note When set to 1, the Channel number field selects the DMA channel to debug. DBGINST1 3.3.21. Debug Instruction-1 Register The DBGINST1 Register characteristics are: Purpose Controls the upper bytes of the debug instruction for the DMAC. See Issuing instructions to the DMAC using an APB interface for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO instruction_byte_5 instruction byte 5 instruction_byte_4 instruction byte 4 instruction_byte_3 instruction byte 3 instruction_byte_2 instruction byte 2 CR0 3.3.22. Configuration Register 0 The CR0 Register characteristics are: Purpose Provides the status of the tie-off control signals. It contains the following information about the configuration of the DMAC: * The number of DMA channels that it contains. * The number of peripheral request interfaces it provides. * The number of irq signals it provides. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO num_events Number of interrupt outputs that the DMAC provides: 0b00000 = 1 interrupt output, irq[0] 0b00001 = 2 interrupt outputs, irq[1:0] 0b00010 = 3 interrupt outputs, irq[2:0] . . . 0b11111 = 32 interrupt outputs, irq[31:0]. num_periph_req Number of peripheral request interfaces that the DMAC provides: 0b00000 = 1 peripheral request interface 0b00001 = 2 peripheral request interfaces 0b00010 = 3 peripheral request interfaces . . . 0b11111 = 32 peripheral request interfaces. Note This field is only valid when the periph_req bit is set to 1. num_chnls Number of DMA channels that the DMAC supports: 0b000 = 1 DMA channel 0b001 = 2 DMA channels 0b010 = 3 DMA channels . . . 0b111 = 8 DMA channels. mgr_ns_at_rst Indicates the status of the boot_manager_ns signal when the DMAC exited from reset: 0 = boot_manager_ns was LOW 1 = boot_manager_ns was HIGH. boot_en Indicates the status of the boot_from_pc signal when the DMAC exited from reset: 0 = boot_from_pc was LOW 1 = boot_from_pc was HIGH. periph_req Supports peripheral requests: 0 = the DMAC does not provide a peripheral request interface 1 = the DMAC provides the number of peripheral request interfaces that the num_periph_req field specifies. CR1 3.3.23. Configuration Register 1 The CR1 Register characteristics are: Purpose Provides information about the instruction cache configuration. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO num_icache_lines Number of i-cache lines: 0b0000 = 1 i-cache line 0b0001 = 2 i-cache lines 0b0010 = 3 i-cache lines . . . 0b1111 = 16 i-cache lines. icache_len The length of an i-cache line: 0b000-0b001 = reserved 0b010 = 4 bytes 0b011 = 8 bytes 0b100 = 16 bytes 0b101 = 32 bytes 0b110-0b111 = reserved. CR2 3.3.24. Configuration Register 2 The CR2 Register characteristics are: Purpose Provides the value of the boot address that boot_addr[31:0] configures. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO boot_addr Provides the value of boot_addr[31:0] when the DMAC exited from reset CR3 3.3.25. Configuration Register 3 The CR3 Register characteristics are: Purpose Provides the security state of the event-interrupt resources that are initialized when the DMAC exits from reset. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO INS Provides the security state of an event-interrupt resource: Bit [N] = 0 Event<N> or irq[N] is in the Secure state. Bit [N] = 1 Event<N> or irq[N] is in the Non-secure state. Note The boot_irq_ns[x:0] signals initialize the bits in this register when the DMAC exits from reset. See Table A.12 for more information. MSB is INS forevent-interrupt[31] LSB is INS forevent-interrupt[0] CR4 3.3.26. Configuration Register 4 The CR4 Register characteristics are: Purpose Provides the security state of the peripheral request interfaces that is initialized when the DMAC exits from reset. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO PNS Provides the security state of the peripheral request interfaces: Bit [N] = 0 Peripheral request interface N is in the Secure state. Bit [N] = 1 Peripheral request interface N is in the Non-secure state. Note The boot_periph_ns tie-off signals initialize the bits in this register when the DMAC exits from reset. See Table A.12 for more information. MSB is PNS for PRPHL_REQ 31 LSB is PNS for PRPHL_REQ 0 CRD 3.3.27. DMA Configuration Register The CRD Register characteristics are: Purpose Provides information about the configuration of the data buffer, data width, and read and write issuing capability of the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO data_buffer_dep The number of lines that the data buffer contains: 0b000000000 = 1 line 0b000000001 = 2 lines . . . 0b111111111 = 1024 lines. rd_q_dep The depth of the read queue: 0b0000 = 1 line 0b0001 = 2 lines . . . 0b1111 = 16 lines. rd_cap Read issuing capability that programs the number of outstanding read transactions: 0b000 = 1 0b001 = 2 . . . 0b111 = 8. wr_q_dep The depth of the write queue: 0b0000 = 1 line 0b0001 = 2 lines . . . 0b1111 = 16 lines. wr_cap Write issuing capability that programs the number of outstanding write transactions: 0b000 = 1 0b001 = 2 . . . 0b111 = 8. data_width The data bus width of the AXI master interface: 0b000 = reserved 0b001 = reserved 0b010 = 32-bit 0b011 = 64-bit 0b100 = 128-bit 0b101-b111 = reserved. WD 3.3.28. Watchdog Register The WD Register characteristics are: Purpose Controls the watchdog behavior. Usage constraints ARM recommends that you only update this register when all the DMA channel threads are in the Stopped state. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RW / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RW wd_irq_only Controls how the DMAC responds when it detects a lock-up condition: 0 = the DMAC aborts all of the contributing DMA channels and sets irq_abort HIGH 1 = the DMAC sets irq_abort HIGH. See Watchdog abort for more information. periph_id_0 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 0) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 0 The periph_id_0 Register is hard-coded and the fields in the register control the reset value. part_number_0 Returns 0x30 periph_id_1 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 1) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 1 The periph_id_1 Register is hard-coded and the fields in the register control the reset value. designer_0 Returns 0x1 part_number_1 Returns 0x3 periph_id_2 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 2) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 2 The periph_id_2 Register is hard-coded and the fields in the register control the reset value. revision Identifies the revision: 0x0 for r0p0. 0x1 for r1p0. 0x2 for r1p1. 0x3 for r1p2. designer_1 Returns 0x4 periph_id_3 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 3) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 3 The periph_id_3 Register is hard-coded and the fields in the register control the reset value. integration_cfg Returns 0 to indicate that the DMAC does not contain integration test logic pcell_id_0 3.3.30. Component Identification Registers 0-3 (pcell_id_0) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_0 Returns 0x0D pcell_id_1 3.3.30. Component Identification Registers 0-3 (pcell_id_1) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_1 Returns 0xF0 pcell_id_2 3.3.30. Component Identification Registers 0-3 (pcell_id_2) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_2 Returns 0x05 pcell_id_3 3.3.30. Component Identification Registers 0-3 (pcell_id_3) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_3 Returns 0xB1 dmasecure Address space allocated to the secure DMA. For detailed information about the use of this address space, [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html]click here[/url] to access the ARM documentation for the DMA-330. DSR 3.3.1. DMA Manager Status Register The DSR Register characteristics are: Purpose Returns information about the status of the DMA manager thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO DNS Provides the security status of the DMA manager thread: 0 = DMA manager operates in the Secure state 1 = DMA manager operates in the Non-secure state. Note You must use the boot_manager_ns signal to set the secure state of the DMA manager thread. Wakeup_event When the DMA manager thread executes a DMAWFE instruction, it waits for the following event to occur: b00000 = event[0] b00001 = event[1] b00010 = event[2] . . . b11111 = event[31]. DMA_status The operating state of the DMA manager: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101-b1110 = reserved b1111 = Faulting. DPC 3.3.2. DMA Program Counter Register The DPC Register characteristics are: Purpose Provides the value of the program counter for the DMA manager thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_mgr Program counter for the DMA manager thread INTEN 3.3.3. Interrupt Enable Register The INTEN Register characteristics are: Purpose When the DMAC executes a DMASEV instruction, each bit of the INTEN Register controls if the DMAC signals: The specified event to all of the threads. An interrupt using the corresponding irq. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RW / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RW event_irq_select Program the appropriate bit to control how the DMAC responds when it executes DMASEV: Bit [N] = 0 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC signals event N to all of the threads. Set bit [N] to 0 if your system design does not use irq[N] to signal an interrupt request. Bit [N] = 1 If the DMAC executes DMASEV for the event-interrupt resource N then the DMAC sets irq[N] HIGH. Set bit [N] to 1 if your system design requires irq[N] to signal an interrupt request. Note See DMASEV for information about selecting an event number. MSB is event_irq_select for event 31 LSB is event_irq_select for event 0 INT_EVENT_RIS 3.3.4. Event-Interrupt Raw Status Register The INT_EVENT_RIS Register characteristics are: Purpose Returns the status of the event-interrupt resources. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO DMASEV_active Returns the status of the event-interrupt resources: Bit [N] = 0 Event N is inactive or irq[N] is LOW. Bit [N] = 1 Event N is active or irq[N] is HIGH. Note When the DMAC executes a DMASEV N instruction to send event N, the INTEN Register controls whether the DMAC: * Signals an interrupt using the appropriate irq. * Sends the event to all of the threads. Note The DMAC clears bit [N] when either: * The INTEN Register is programmed to process the event and the DMAC executes a DMAWFE instruction for that event. * The INTEN Register is programmed to signal an interrupt and you write to the corresponding bit in the INTCLR Register, see Interrupt Clear Register. MSB is DMASEV [31] active LSB is DMASEV [0] active INTMIS 3.3.5. Interrupt Status Register The INTMIS Register characteristics are: Purpose Provides the status of the active interrupts in the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO irq_status Provides the status of the interrupts that are active in the DMAC: Bit [N] = 0 Interrupt N is inactive and therefore irq[N] is LOW. Bit [N] = 1 Interrupt N is active and therefore irq[N] is HIGH. Note You must use the INTCLR Register to set bit [N] to 0, see Interrupt Clear Register. Note Bit [N] is 0 if the INTEN Register programs DMASEV to signal an event, see Interrupt Enable Register. MSB is irq_status for irq[31] LSB is irq_status for irq[0] INTCLR 3.3.6. Interrupt Clear Register The INTCLR Register characteristics are: Purpose Provides the status of the active interrupts in the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO irq_clr Controls the clearing of the irq outputs: Bit [N] = 0 The status of irq[N] does not change. Bit [N] = 1 The DMAC sets irq[N] LOW if the INTEN Register programs the DMAC to signal an interrupt. Otherwise, the status of irq[N] does not change. See Interrupt Enable Register. MSB is irq_clr for irq[31] LSB is irq_clr for irq[0] FSRD 3.3.7. Fault Status DMA Manager Register The FSRD Register characteristics are: Purpose Provides the fault status of the DMA manager. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO fs_mgr Provides the fault status of the DMA manager. Read as: 0 = the DMA manager thread is not in the Faulting state 1 = the DMA manager thread is in the Faulting state. See Fault Type DMA Manager Register for information about the type of fault that occurred. FSRC 3.3.8. Fault Status DMA Channel Register The FSRC Register characteristics are: Purpose Provides the fault status for the DMA channels. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO fault_status Each bit provides the fault status of the corresponding channel. Read as: Bit [N] = 0 No fault is present on DMA channel N. Bit [N] = 1 DMA channel N is in the Faulting or Faulting completing state. See Fault Type DMA Channel Registers for information about the type of fault that occurred. MSB is fault_status for DMA channel 7 LSB is fault_status for DMA channel 0 FTRD 3.3.9. Fault Type DMA Manager Register The FTRD Register characteristics are: Purpose Provides the type of fault that occurred to move the DMA manager to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dbg_instr If the DMA manager aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA manager performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. mgr_evnt_err Indicates whether the DMA manager was attempting to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = the DMA manager has appropriate security to execute DMAWFE or DMASEV 1 = a DMA manager thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. dmago_err Indicates whether the DMA manager was attempting to execute DMAGO with inappropriate security permissions: 0 = the DMA manager has appropriate security to execute DMAGO 1 = a DMA manager thread in the Non-secure state attempted to execute DMAGO to create a DMA channel operating in the Secure state. operand_invalid Indicates whether the DMA manager was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. undef_instr Indicates whether the DMA manager was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. FTR0 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 0) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR1 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 1) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR2 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 2) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR3 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 3) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR4 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 4) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR5 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 5) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR6 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 6) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. FTR7 3.3.10. Fault Type DMA Channel Registers (Fault type for DMA channel 7) The FTRn Register characteristics are: Purpose Provides the type of fault that occurred to move a DMA channel to the Faulting state. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a FTRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Depending on the fault type, the DMAC abort is categorized as: Precise abort With the thread in the faulting state, you can read the CPCn Register to determine the value of the program counter that caused the fault to occur. See Channel Program Counter Registers. Imprecise abort The program counter register, CPCn Register, does not contain the address of the instruction that caused the fault to occur. See Channel Program Counter Registers. lockup_err Indicates whether the DMA channel has locked-up because of resource starvation: 0 = DMA channel has adequate resources 1 = DMA channel has locked-up because of insufficient resources. This fault is an imprecise abort. dbg_instr If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface: 0 = instruction that generated an abort was read from system memory 1 = instruction that generated an abort was read from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. data_read_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. data_write_err Indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is an imprecise abort. instr_fetch_err Indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch: 0 = OKAY response 1 = EXOKAY, SLVERR, or DECERR response. This fault is a precise abort. st_data_unavailable Indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST: 0 = MFIFO contains all the data to enable the DMAST to complete 1 = previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. This fault is a precise abort. mfifo_err Indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction: DMALD 0 = MFIFO contains sufficient space 1 = MFIFO is too small to hold the data that DMALD requires. DMAST 0 = MFIFO contains sufficient data 1 = MFIFO is too small to store the data to enable DMAST to complete. This fault is an imprecise abort. ch_rdwr_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to program the CCRn Register to perform a secure read or secure write: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to perform a secure read or secure write. This fault is a precise abort. ch_periph_err Indicates whether a DMA channel thread, in the Non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFP to wait for a secure peripheral. * DMALDP or DMASTP to notify a secure peripheral. * DMAFLUSHP to flush a secure peripheral. This fault is a precise abort. ch_evnt_err Indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions: 0 = a DMA channel thread in the Non-secure state is not violating the security permissions 1 = a DMA channel thread in the Non-secure state attempted to execute either: * DMAWFE to wait for a secure event. * DMASEV to create a secure event or secure interrupt. This fault is a precise abort. operand_invalid Indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC: 0 = valid operand 1 = invalid operand. This fault is a precise abort. undef_instr Indicates whether the DMA channel thread was attempting to execute an undefined instruction: 0 = defined instruction 1 = undefined instruction. This fault is a precise abort. CSR0 3.3.11. Channel Status Registers (Channel status for DMA channel 0) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC0 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 0) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR1 3.3.11. Channel Status Registers (Channel status for DMA channel 1) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC1 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 1) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR2 3.3.11. Channel Status Registers (Channel status for DMA channel 2) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC2 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 2) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR3 3.3.11. Channel Status Registers (Channel status for DMA channel 3) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC3 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 3) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR4 3.3.11. Channel Status Registers (Channel status for DMA channel 4) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC4 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 4) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR5 3.3.11. Channel Status Registers (Channel status for DMA channel 5) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC5 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 5) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR6 3.3.11. Channel Status Registers (Channel status for DMA channel 6) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC6 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 6) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. CSR7 3.3.11. Channel Status Registers (Channel status for DMA channel 7) The CSRn Register characteristics are: Purpose Provides the status of the DMA program on a DMA channel. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CSRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO CNS The channel non-secure bit provides the security of the DMA channel: 0 = DMA channel operates in the Secure state 1 = DMA channel operates in the Non-secure state. Note The DMAGO instruction determines the security state of a DMA channel. See DMAGO. dmawfp_periph When the DMA channel thread executes DMAWFP, this bit indicates whether the periph operand was set: 0 = DMAWFP executed with the periph operand not set 1 = DMAWFP executed with the periph operand set. See DMAWFP. dmawfp_b_ns When the DMA channel thread executes DMAWFP, this bit indicates whether the burst or single operand were set: 0 = DMAWFP executed with the single operand set 1 = DMAWFP executed with the burst operand set. See DMAWFP. Wakeup_number If the DMA channel is in the Waiting for event state, or the Waiting for peripheral state, then these bits indicate the event or peripheral number that the channel is waiting for: b00000 = DMA channel is waiting for event, or peripheral, 0 b00001 = DMA channel is waiting for event, or peripheral, 1 b00010 = DMA channel is waiting for event, or peripheral, 2 . . . b11111 = DMA channel is waiting for event, or peripheral, 31. Channel_status The channel status encoding is: b0000 = Stopped b0001 = Executing b0010 = Cache miss b0011 = Updating PC b0100 = Waiting for event b0101 = At barrier b0110 = reserved b0111 = Waiting for peripheral b1000 = Killing b1001 = Completing b1010-b1101 = reserved b1110 = Faulting completing b1111 = Faulting. See Operating states for more information. CPC7 3.3.12. Channel Program Counter Registers (Channel PC for DMA channel 7) The CPCn Register characteristics are: Purpose Provides the value of the program counter for the DMA channel thread. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CPCn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO pc_chnl Program counter for the DMA channel n thread, where n depends on the address of the register. SAR0 3.3.13. Source Address Registers (Source address for DMA channel 0) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR0 3.3.14. Destination Address Registers (Destination address for DMA channel 0) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR0 3.3.15. Channel Control Registers (Channel control for DMA channel 0) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_0 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 0) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_0 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 0) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR1 3.3.13. Source Address Registers (Source address for DMA channel 1) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR1 3.3.14. Destination Address Registers (Destination address for DMA channel 1) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR1 3.3.15. Channel Control Registers (Channel control for DMA channel 1) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_1 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 1) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_1 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 1) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR2 3.3.13. Source Address Registers (Source address for DMA channel 2) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR2 3.3.14. Destination Address Registers (Destination address for DMA channel 2) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR2 3.3.15. Channel Control Registers (Channel control for DMA channel 2) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_2 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 2) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_2 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 2) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR3 3.3.13. Source Address Registers (Source address for DMA channel 3) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR3 3.3.14. Destination Address Registers (Destination address for DMA channel 3) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR3 3.3.15. Channel Control Registers (Channel control for DMA channel 3) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_3 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 3) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_3 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 3) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR4 3.3.13. Source Address Registers (Source address for DMA channel 4) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR4 3.3.14. Destination Address Registers (Destination address for DMA channel 4) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR4 3.3.15. Channel Control Registers (Channel control for DMA channel 4) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_4 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 4) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_4 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 4) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR5 3.3.13. Source Address Registers (Source address for DMA channel 5) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR5 3.3.14. Destination Address Registers (Destination address for DMA channel 5) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR5 3.3.15. Channel Control Registers (Channel control for DMA channel 5) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_5 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 5) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_5 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 5) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR6 3.3.13. Source Address Registers (Source address for DMA channel 6) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR6 3.3.14. Destination Address Registers (Destination address for DMA channel 6) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR6 3.3.15. Channel Control Registers (Channel control for DMA channel 6) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_6 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 6) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_6 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 6) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations SAR7 3.3.13. Source Address Registers (Source address for DMA channel 7) The SARn Register characteristics are: Purpose Provides the address of the source data for a DMA channel. The DMAC writes the initial source address value to the SA Register when the DMA channel thread executes a DMAMOV SAR instruction. If a DMAMOV CCR instruction programs the source address to increment, each time the DMA channel executes DMALD, it updates the value to indicate the address that the next DMALD must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a SARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO src_addr Address of the source data for DMA channel n, where n depends on the address of the register. DAR7 3.3.14. Destination Address Registers (Destination address for DMA channel 7) The DARn Register characteristics are: Purpose Provides the address for the destination data for a DMA channel. The DMAC writes the initial destination address value to the DA Register when the DMA channel thread executes a DMAMOV DAR instruction. If a subsequent DMAMOV CCR instruction programs the destination address to increment, then each time the DMA channel executes DMAST, it updates the value to indicate the address that the next DMAST must use. See DMAMOV for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a DARn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dst_addr Address for the destination data for DMA channel n, where n depends on the address of the register. CCR7 3.3.15. Channel Control Registers (Channel control for DMA channel 7) The CCRn Register characteristics are: Purpose Controls the AXI transactions that the DMAC uses for a DMA channel. The DMAC writes to the corresponding CC Register when a DMA channel thread executes a DMAMOV CCR instruction. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a CCRn Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO endian_swap_size Endian swap size Table 3.22 defines whether data can be swapped between little-endian (LE) and byte-invariant big-endian (BE-8) formats, and if so, also defines the natural width of the data independently of the source and destination transaction sizes. This enables unaligned data streams to use the full bus-width, and to be correctly transformed, irrespective of the source and destination address alignments. The format is identical to AxSIZE, except that 0b000 indicates that no swap must occur. Table 3.22. Swap data +------------------+-------------------------------------+ | Endian swap size | Description | +------------------+-------------------------------------+ | 0b000 | No swap, 8-bit data | | 0b001 | Swap bytes within 16-bit data | | 0b010 | Swap bytes within 32-bit data | | 0b011 | Swap bytes within 64-bit data | | 0b100 | Swap bytes within 128-bit data | | 0b101 | Reserved | | 0b110 | Reserved | | 0b111 | Reserved | +------------------+-------------------------------------+ Note See Endian swap size restrictions for information about some restrictions that apply when you use this feature. dst_cache_ctrl Programs the state of AWCACHE[3,1:0] when the DMAC writes the destination data. Bit [27] 0 = AWCACHE[3] is LOW 1 = AWCACHE[3] is HIGH. Bit [26] 0 = AWCACHE[1] is LOW 1 = AWCACHE[1] is HIGH. Bit [25] 0 = AWCACHE[0] is LOW 1 = AWCACHE[0] is HIGH. Note AWCACHE[2] is tied LOW by the DMAC. Setting AWCACHE[3,1]=b10 violates the AXI protocol. See the AMBA AXI Protocol Specification. dst_prot_ctrl Programs the state of AWPROT[2:0] when the DMAC writes the destination data. Bit [24] 0 = AWPROT[2] is LOW 1 = AWPROT[2] is HIGH. Bit [23] 0 = AWPROT[1] is LOW 1 = AWPROT[1] is HIGH. Bit [22] 0 = AWPROT[0] is LOW 1 = AWPROT[0] is HIGH. Note Only DMA channels in the Secure state can program AWPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set AWPROT[1] LOW, then the DMA channel aborts. dst_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it writes the destination data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWLEN[3:0]. dst_burst_size For each beat within a burst, it programs the number of bytes that the DMAC writes to the destination: 0b000 = writes 1 byte per beat 0b001 = writes 2 bytes per beat 0b010 = writes 4 bytes per beat 0b011 = writes 8 bytes per beat 0b100 = writes 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC writes out of the MFIFO when it executes a DMAST instruction is the product of dst_burst_len and dst_burst_size. Note These bits control the state of AWSIZE[2:0]. dst_inc Programs the burst type that the DMAC performs when it writes the destination data: 0 = Fixed-address burst. The DMAC signals AWBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals AWBURST[0] HIGH. src_cache_ctrl Set the bits to control the state of ARCACHE[2:0] when the DMAC reads the source data. Bit [13] 0 = ARCACHE[2] is LOW 1 = ARCACHE[2] is HIGH. Bit [12] 0 = ARCACHE[1] is LOW 1 = ARCACHE[1] is HIGH. Bit [11] 0 = ARCACHE[0] is LOW 1 = ARCACHE[0] is HIGH. Note The DMAC ties ARCACHE[3] LOW. Setting ARCACHE[2:1]=b10 violates the AXI protocol. See the AMBA AXI and ACE Protocol Specification. src_prot_ctrl Programs the state of ARPROT[2:0] when the DMAC reads the source data. Bit [10] 0 = ARPROT[2] is LOW 1 = ARPROT[2] is HIGH. Bit [9] 0 = ARPROT[1] is LOW 1 = ARPROT[1] is HIGH. Bit [8] 0 = ARPROT[0] is LOW 1 = ARPROT[0] is HIGH. Note Only DMA channels in the Secure state can program ARPROT[1] LOW, that is, a secure access. If a DMA channel in the Non-secure state attempts to set ARPROT[1] LOW, the DMA channel aborts. src_burst_len For each burst, these bits program the number of data transfers that the DMAC performs when it reads the source data: 0b0000 = 1 data transfer 0b0001 = 2 data transfers 0b0010 = 3 data transfers . . . 0b1111 = 16 data transfers. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARLEN[3:0]. src_burst_size For each beat within a burst, it programs the number of bytes that the DMAC reads from the source: 0b000 = reads 1 byte per beat 0b001 = reads 2 bytes per beat 0b010 = reads 4 bytes per beat 0b011 = reads 8 bytes per beat 0b100 = reads 16 bytes per beat 0b101-0b111 = reserved. The total number of bytes that the DMAC reads into the MFIFO when it executes a DMALD instruction is the product of src_burst_len and src_burst_size. Note These bits control the state of ARSIZE[2:0]. src_inc Programs the burst type that the DMAC performs when it reads the source data: 0 = Fixed-address burst. The DMAC signals ARBURST[0] LOW. 1 = Incrementing-address burst. The DMAC signals ARBURST[0] HIGH. LC0_7 3.3.16. Loop Counter 0 Registers (Loop counter 0 for DMA channel 7) The LC0_n Register characteristics are: Purpose Provides the status of loop counter zero for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter zero. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC0_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations LC1_7 3.3.17. Loop Counter 1 Registers (Loop counter 1 for DMA channel 7) The LC1_n Register characteristics are: Purpose Provides the status of loop counter one for the DMA channel. The DMAC updates this register when it executes DMALPEND[S|B], and the DMA channel thread is programmed to use loop counter one. See DMALPEND[S|B]. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. The DMAC provides a LC1_n Register for each DMA channel that it contains. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO Loop_counter_iterations The number of loop counter iterations DBGSTATUS 3.3.18. Debug Status Register The DBGSTATUS Register characteristics are: Purpose Provides the debug status of the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO dbgstatus The debug status encoding is: 0 = Idle 1 = Busy. DBGCMD 3.3.19. Debug Command Register The DBGCMD Register characteristics are: Purpose Controls the execution of debug commands in the DMAC as Issuing instructions to the DMAC using an APB interface describes. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO dbgcmd The debug encoding is as follows: 0b00 = execute the instruction that the DBGINST [1:0] Registers contain 0b01 = reserved 0b10 = reserved 0b11 = reserved. DBGINST0 3.3.20. Debug Instruction-0 Register The DBGINST0 Register characteristics are: Purpose Controls the debug instruction, channel, and thread information for the DMAC. See Issuing instructions to the DMAC using an APB interface for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO instruction_byte_1 instruction byte 1. instruction_byte_0 instruction byte 0. Channel_number DMA channel number: 0b000 = DMA channel 0 0b001 = DMA channel 1 0b010 = DMA channel 2 . . . 0b111 = DMA channel 7. Debug_thread The debug thread encoding is as follows: 0 = DMA manager thread 1 = DMA channel. Note When set to 1, the Channel number field selects the DMA channel to debug. DBGINST1 3.3.21. Debug Instruction-1 Register The DBGINST1 Register characteristics are: Purpose Controls the upper bytes of the debug instruction for the DMAC. See Issuing instructions to the DMAC using an APB interface for more information. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:WO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:WO instruction_byte_5 instruction byte 5 instruction_byte_4 instruction byte 4 instruction_byte_3 instruction byte 3 instruction_byte_2 instruction byte 2 CR0 3.3.22. Configuration Register 0 The CR0 Register characteristics are: Purpose Provides the status of the tie-off control signals. It contains the following information about the configuration of the DMAC: * The number of DMA channels that it contains. * The number of peripheral request interfaces it provides. * The number of irq signals it provides. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO num_events Number of interrupt outputs that the DMAC provides: 0b00000 = 1 interrupt output, irq[0] 0b00001 = 2 interrupt outputs, irq[1:0] 0b00010 = 3 interrupt outputs, irq[2:0] . . . 0b11111 = 32 interrupt outputs, irq[31:0]. num_periph_req Number of peripheral request interfaces that the DMAC provides: 0b00000 = 1 peripheral request interface 0b00001 = 2 peripheral request interfaces 0b00010 = 3 peripheral request interfaces . . . 0b11111 = 32 peripheral request interfaces. Note This field is only valid when the periph_req bit is set to 1. num_chnls Number of DMA channels that the DMAC supports: 0b000 = 1 DMA channel 0b001 = 2 DMA channels 0b010 = 3 DMA channels . . . 0b111 = 8 DMA channels. mgr_ns_at_rst Indicates the status of the boot_manager_ns signal when the DMAC exited from reset: 0 = boot_manager_ns was LOW 1 = boot_manager_ns was HIGH. boot_en Indicates the status of the boot_from_pc signal when the DMAC exited from reset: 0 = boot_from_pc was LOW 1 = boot_from_pc was HIGH. periph_req Supports peripheral requests: 0 = the DMAC does not provide a peripheral request interface 1 = the DMAC provides the number of peripheral request interfaces that the num_periph_req field specifies. CR1 3.3.23. Configuration Register 1 The CR1 Register characteristics are: Purpose Provides information about the instruction cache configuration. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO num_icache_lines Number of i-cache lines: 0b0000 = 1 i-cache line 0b0001 = 2 i-cache lines 0b0010 = 3 i-cache lines . . . 0b1111 = 16 i-cache lines. icache_len The length of an i-cache line: 0b000-0b001 = reserved 0b010 = 4 bytes 0b011 = 8 bytes 0b100 = 16 bytes 0b101 = 32 bytes 0b110-0b111 = reserved. CR2 3.3.24. Configuration Register 2 The CR2 Register characteristics are: Purpose Provides the value of the boot address that boot_addr[31:0] configures. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO boot_addr Provides the value of boot_addr[31:0] when the DMAC exited from reset CR3 3.3.25. Configuration Register 3 The CR3 Register characteristics are: Purpose Provides the security state of the event-interrupt resources that are initialized when the DMAC exits from reset. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO INS Provides the security state of an event-interrupt resource: Bit [N] = 0 Event<N> or irq[N] is in the Secure state. Bit [N] = 1 Event<N> or irq[N] is in the Non-secure state. Note The boot_irq_ns[x:0] signals initialize the bits in this register when the DMAC exits from reset. See Table A.12 for more information. MSB is INS forevent-interrupt[31] LSB is INS forevent-interrupt[0] CR4 3.3.26. Configuration Register 4 The CR4 Register characteristics are: Purpose Provides the security state of the peripheral request interfaces that is initialized when the DMAC exits from reset. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO PNS Provides the security state of the peripheral request interfaces: Bit [N] = 0 Peripheral request interface N is in the Secure state. Bit [N] = 1 Peripheral request interface N is in the Non-secure state. Note The boot_periph_ns tie-off signals initialize the bits in this register when the DMAC exits from reset. See Table A.12 for more information. MSB is PNS for PRPHL_REQ 31 LSB is PNS for PRPHL_REQ 0 CRD 3.3.27. DMA Configuration Register The CRD Register characteristics are: Purpose Provides information about the configuration of the data buffer, data width, and read and write issuing capability of the DMAC. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RO / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RO data_buffer_dep The number of lines that the data buffer contains: 0b000000000 = 1 line 0b000000001 = 2 lines . . . 0b111111111 = 1024 lines. rd_q_dep The depth of the read queue: 0b0000 = 1 line 0b0001 = 2 lines . . . 0b1111 = 16 lines. rd_cap Read issuing capability that programs the number of outstanding read transactions: 0b000 = 1 0b001 = 2 . . . 0b111 = 8. wr_q_dep The depth of the write queue: 0b0000 = 1 line 0b0001 = 2 lines . . . 0b1111 = 16 lines. wr_cap Write issuing capability that programs the number of outstanding write transactions: 0b000 = 1 0b001 = 2 . . . 0b111 = 8. data_width The data bus width of the AXI master interface: 0b000 = reserved 0b001 = reserved 0b010 = 32-bit 0b011 = 64-bit 0b100 = 128-bit 0b101-b111 = reserved. WD 3.3.28. Watchdog Register The WD Register characteristics are: Purpose Controls the watchdog behavior. Usage constraints ARM recommends that you only update this register when all the DMA channel threads are in the Stopped state. Configurations Available in all configurations of the DMAC. Attributes Secure accress:RW / Non-secure access when thread is secure:RAZ / Non-secure access when thread is secure:RW wd_irq_only Controls how the DMAC responds when it detects a lock-up condition: 0 = the DMAC aborts all of the contributing DMA channels and sets irq_abort HIGH 1 = the DMAC sets irq_abort HIGH. See Watchdog abort for more information. periph_id_0 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 0) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 0 The periph_id_0 Register is hard-coded and the fields in the register control the reset value. part_number_0 Returns 0x30 periph_id_1 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 1) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 1 The periph_id_1 Register is hard-coded and the fields in the register control the reset value. designer_0 Returns 0x1 part_number_1 Returns 0x3 periph_id_2 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 2) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 2 The periph_id_2 Register is hard-coded and the fields in the register control the reset value. revision Identifies the revision: 0x0 for r0p0. 0x1 for r1p0. 0x2 for r1p1. 0x3 for r1p2. designer_1 Returns 0x4 periph_id_3 3.3.29. Peripheral Identification Registers (Peripheral Identification Register 3) The periph_id_[3:0] Register characteristics are: Purpose Provides information about the configuration and version of the peripheral. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO Peripheral Identification Register 3 The periph_id_3 Register is hard-coded and the fields in the register control the reset value. integration_cfg Returns 0 to indicate that the DMAC does not contain integration test logic pcell_id_0 3.3.30. Component Identification Registers 0-3 (pcell_id_0) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_0 Returns 0x0D pcell_id_1 3.3.30. Component Identification Registers 0-3 (pcell_id_1) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_1 Returns 0xF0 pcell_id_2 3.3.30. Component Identification Registers 0-3 (pcell_id_2) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_2 Returns 0x05 pcell_id_3 3.3.30. Component Identification Registers 0-3 (pcell_id_3) The pcell_id_[3:0] Register characteristics are: Purpose When concatenated, these four registers return 0xB105F00D. Usage constraints No usage constraints. Configurations Available in all configurations of the DMAC. Attributes RO pcell_id_3 Returns 0xB1