default_vendor_com addon ARM IP registers. Address map for the HHP HPS system-domain mpul2 This address space is allocated to the MPU L2 cache controller. For detailed information about the use of this address space, [url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/index.html]click here[/url] to access the ARM documentation for the L2C-310. reg0_cache_id 3.3.1 Cache ID Register The reg0_cache_id Register characteristics are: Purpose Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RO Implementer 0x41 ARM CACHE_ID - Part_number 0x3 RTL_release 0x9 reg0_cache_type 3.3.2 Cache Type Register The reg0_cache_type Register characteristics are: Purpose Returns the 32-bit cache type. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RO Data_banking 0 = data banking not implemented 1 = data banking implemented ctype 0b11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. See Cache lockdown on page 3-27. H 0 = unified 1 = Harvard Dsize bit[23] SBZ/RAZ bit[22:20] L2 cache way size: Read from Auxiliary Control Register[19:17] bit[19] SBZ/RAZ L2_associativity_D Read from Auxiliary Control Register[16] L2_cache_line_length_D 0b00: 32bytes Isize bit[11] SBZ/RAZ bit[10:8] L2 cache way size: Read from Auxiliary Control Register[19:17] bit[7] SBZ/RAZ L2_associativity_I Read from Auxiliary Control Register[16] L2_cache_line_length_I 0b00: 32bytes reg1_control 3.3.3 Control Register The reg1_control Register characteristics are: Purpose Enables or disables the cache controller. Usage constraints This register enables or disables the cache controller. Must be written using a secure access. It can be read using either a secure or a NS access. Writing to this register with a NS access causes a write response signal with a DECERR response, and the register is not updated, only permitting a secure access to enable or disable the cache controller. When receiving a transaction to enable or disable the cache by modifying this register the cache controller follows the described sequence. This prevents any unpredictable behavior if there are subsequent writes to any of the L2 registers. 1. Lock slave ports and wait for all outstanding transactions to complete and all buffers to be empty by performing a cache sync. 2. Update register. 3. Return write response. Configurations Available in all configurations. Attributes RW L2_Cache_enable 0 = L2 Cache is disabled. This is the default value. 1 = L2 Cache is enabled. reg1_aux_control 3.3.4 Auxiliary Control Register The reg1_aux_control Register characteristics are: Purpose Configures: • cache behavior • event monitoring • way size • associativity. Usage constraints The register must be written to using a secure access and with its reserved bits preserved. You can read it using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is bit[0] of L2 Control Register set to 1, results in a SLVERR. The DECERR response has priority over the SLVERR response. Configurations Available in all configurations. Attributes RW Early_BRESP_enable 0 = Early BRESP disabled. This is the default. 1 = Early BRESP enabled. See Early write response on page 2-37. Instruction_prefetch_enable 0 = Instruction prefetching disabled. This is the default. 1 = Instruction prefetching enabled. See Prefetch Control Register on page 3-34. Data_prefetch_enable 0 = Data prefetching disabled. This is the default. 1 = Data prefetching enabled. See Prefetch Control Register on page 3-34. Nonsecure_interrupt_access_control 0 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can only be modified or read with secure accesses. This is the default. 1 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can be modified or read with secure or non-secure accesses. Nonsecure_lockdown_enable 0 = Lockdown registers cannot be modified using non-secure accesses. This is the default. 1 = Non-secure accesses can write to the lockdown registers. Cache_replacement_policy 0 = Pseudo-random replacement using lfsr. 1 = Round-robin replacement. This is the default. See Replacement strategy on page 3-31. Force_write_allocate 0b00 = Use AWCACHE attributes for WA. This is the default. 0b01 = Force no allocate, set WA bit always 0. 0b10 = Override AWCACHE attributes, set WA bit always 1, all cacheable write misses become write allocated. 0b11 = Internally mapped to 00. See Cache operation on page 2-11 for more information. Shared_attribute_override_enable 0 = Treats shared accesses as specified in Shareable attribute on page 2-15. This is the default. 1 = Shared attribute internally ignored. Parity_enable 0 = Disabled. This is the default. 1 = Enabled. Event_monitor_bus_enable 0 = Disabled. This is the default. 1 = Enabled. Way_size 0b000 = Reserved, internally mapped to 16KB. 0b001 = 16KB 0b010 = 32KB 0b011 = 64KB 0b100 = 128KB 0b101 = 256KB 0b110 = 512KB 0b111 = Reserved, internally mapped to 512 KB. Associativity 0 = 8-way 1 = 16-way. Shared_Attribute_Invalidate_Enable 0 = Shared invalidate behavior disabled. This is the default. 1 = Shared invalidate behavior enabled, if Shared Attribute Override Enable bit not set. See Shareable attribute on page 2-15. Exclusive_cache_configuration 0 = Disabled. This is the default. 1 = Enabled. See Exclusive cache configuration on page 2-17. Store_buffer_device_limitation_Enable 0 = Store buffer device limitation disabled. Device writes can take all slots in store buffer. This is the default. 1 = Store buffer device limitation enabled. Device writes cannot take all slots in store buffer when connected to the Cortex-A9 MPCore processor. There is always one available slot to service Normal Memory. HP_for_SO_and_DR_Enable 0 = Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC L2C-310 master ports. This is the default. 1 = Strongly Ordered and Device reads get the highest priority when arbitrated in the L2C-310 master ports. Full_Line_of_Zero_Enable 0 = Full line of write zero behavior disabled. This is the default. 1 = Full line of write zero behavior Enabled. See Full line of zero write on page 2-37. reg1_tag_ram_control 3.3.5 Tag and Data RAM Latency Control Registers - Tag The reg1_tag_ram_control and reg1_data_ram_control Register characteristics are: Purpose Configures: • Tag RAM latencies for the Tag RAM Latency Control Register • Data RAM latencies for the Data RAM Latency Control Register. Usage constraints The registers must be written using a secure access. They can be read using either a secure or a NS access. If you write to these registers with a NS access, it results in a write response with a DECERR response, and the registers are not updated. Writing to these registers with the L2 cache enabled, that is, bit[0] of the Control Register set to 1, results in a SLVERR. Configurations Available in all configurations. Attributes RW RAM_write_access_latency Default value depends on the value of pl310_TAG_WRITE_LAT for reg1_tag_ram_control or pl310_DATA_WRITE_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. RAM_read_access_latency Default value depends on the value of pl310_TAG_READ_LAT for reg1_tag_ram_control or pl310_DATA_READ_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. RAM_setup_latency Default value depends on the value of pl310_TAG_SETUP_LAT for reg1_tag_ram_control or pl310_DATA_SETUP_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. reg1_data_ram_control 3.3.5 Tag and Data RAM Latency Control Registers - Data The reg1_tag_ram_control and reg1_data_ram_control Register characteristics are: Purpose Configures: • Tag RAM latencies for the Tag RAM Latency Control Register • Data RAM latencies for the Data RAM Latency Control Register. Usage constraints The registers must be written using a secure access. They can be read using either a secure or a NS access. If you write to these registers with a NS access, it results in a write response with a DECERR response, and the registers are not updated. Writing to these registers with the L2 cache enabled, that is, bit[0] of the Control Register set to 1, results in a SLVERR. Configurations Available in all configurations. Attributes RW RAM_write_access_latency Default value depends on the value of pl310_TAG_WRITE_LAT for reg1_tag_ram_control or pl310_DATA_WRITE_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. RAM_read_access_latency Default value depends on the value of pl310_TAG_READ_LAT for reg1_tag_ram_control or pl310_DATA_READ_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. RAM_setup_latency Default value depends on the value of pl310_TAG_SETUP_LAT for reg1_tag_ram_control or pl310_DATA_SETUP_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency. reg2_ev_counter_ctrl 3.3.6 Event Counter Control Register The reg2_ev_counter_ctrl Register characteristics are: Purpose Permits the event counters to be enabled and reset. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RW Counter_reset Always Read as zero. The following counters are reset when a 1 is written to the following bits: • bit[2] = Event Counter1 reset • bit[1] = Event Counter0 reset. Event_counter_enable 0 = Event Counting Disable. This is the default. 1 = Event Counting Enable. reg2_ev_counter1_cfg 3.3.7 Event Counter Configuration Registers - 1 The reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register characteristics are: Purpose Enables event counter 1 and 0 to be driven by a specific event. Counter 1 or counter 0 increments when the event occurs. Cache event monitoring on page 2-42 describes the counter event source signals. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RW Counter_event_source Event : Encoding Counter Disabled : 0b0000 CO : 0b0001 DRHIT : 0b0010 DRREQ : 0b0011 DWHIT : 0b0100 DWREQ : 0b0101 DWTREQ : 0b0110 IRHIT : 0b0111 IRREQ : 0b1000 WA : 0b1001 IPFALLOC : 0b1010 EPFHIT : 0b1011 EPFALLOC : 0b1100 SRRCVD : 0b1101 SRCONF : 0b1110 EPFRCVD : 0b1111 Event_counter_interrupt_gen 0b00 = Disabled. This is the default. 0b01 = Enabled: Increment condition. 0b10 = Enabled: Overflow condition. 0b11 = Interrupt generation is disabled. reg2_ev_counter0_cfg 3.3.7 Event Counter Configuration Registers - 0 The reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register characteristics are: Purpose Enables event counter 1 and 0 to be driven by a specific event. Counter 1 or counter 0 increments when the event occurs. Cache event monitoring on page 2-42 describes the counter event source signals. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RW Counter_event_source Event : Encoding Counter Disabled : 0b0000 CO : 0b0001 DRHIT : 0b0010 DRREQ : 0b0011 DWHIT : 0b0100 DWREQ : 0b0101 DWTREQ : 0b0110 IRHIT : 0b0111 IRREQ : 0b1000 WA : 0b1001 IPFALLOC : 0b1010 EPFHIT : 0b1011 EPFALLOC : 0b1100 SRRCVD : 0b1101 SRCONF : 0b1110 EPFRCVD : 0b1111 Event_counter_interrupt_gen 0b00 = Disabled. This is the default. 0b01 = Enabled: Increment condition. 0b10 = Enabled: Overflow condition. 0b11 = Interrupt generation is disabled. reg2_ev_counter1 3.3.8 Event counter value registers - 1 The reg2_ev_counter0 and reg2_ev_counter1 Register characteristics are: Purpose Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register. Usage constraints Can only be written to when bits [5:2] of the Event Counter Configuration Registers are set to Counter Disabled. Configurations Available in all configurations. Attributes RW Counter_value Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset. reg2_ev_counter0 3.3.8 Event counter value registers - 0 The reg2_ev_counter0 and reg2_ev_counter1 Register characteristics are: Purpose Enable the programmer to read off the counter value. The counter counts an event as specified by the Counter Configuration Registers. The counter can be preloaded if counting is disabled and reset by the Event Counter Control Register. Usage constraints Can only be written to when bits [5:2] of the Event Counter Configuration Registers are set to Counter Disabled. Configurations Available in all configurations. Attributes RW Counter_value Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset. reg2_int_mask 3.3.9 Interrupt registers - Interrupt Mask Register The reg2_int_mask Register characteristics are: Purpose This register enables or masks interrupts from being triggered on the external pins of the cache controller. Figure 3-8 on page 3-17 shows the register bit assignments. The bit assignments enables the masking of the interrupts on both their individual outputs and the combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on that pin. All bits are cleared by a reset. You must write to the register bits with a 1 to enable the generation of interrupts. Usage constraints Non-secure writes to this register are dependent on Auxiliary Control Register bit [27]. If bit [27] of the Auxiliary Control Register is 0, a Non secure write to the Interrupt Mask Register results in a DECERR response. Configurations Available in all configurations. Attributes RW DECERR DECERR: DECERR from L3 0 = Masked. This is the default. 1 = Enabled. SLVERR SLVERR: SLVERR from L3 0 = Masked. This is the default. 1 = Enabled. ERRRD ERRRD: Error on L2 data RAM, Read 0 = Masked. This is the default. 1 = Enabled. ERRRT ERRRT: Error on L2 tag RAM, Read 0 = Masked. This is the default. 1 = Enabled. ERRWD ERRWD: Error on L2 data RAM, Write 0 = Masked. This is the default. 1 = Enabled. ERRWT ERRWT: Error on L2 tag RAM, Write 0 = Masked. This is the default. 1 = Enabled. PARRD PARRD: Parity Error on L2 data RAM, Read 0 = Masked. This is the default. 1 = Enabled. PARRT PARRT: Parity Error on L2 tag RAM, Read 0 = Masked. This is the default. 1 = Enabled. ECNTR ECNTR: Event Counter1 and Event Counter 0 Overflow Increment 0 = Masked. This is the default. 1 = Enabled. reg2_int_mask_status 3.3.9 Interrupt registers - Masked Interrupt Status Register The reg2_int_mask_status Register characteristics are: Purpose This register is a read-only.It returns the masked interrupt status. This register can be accessed by secure and non-secure operations. The register gives an AND function of the raw interrupt status with the values of the interrupt mask register. All the bits are cleared by a reset. A write to this register is ignored. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RO DECERR DECERR: DECERR from L3 Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. SLVERR SLVERR: SLVERR from L3 Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRRD ERRRD: Error on L2 data RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRRT ERRRT: Error on L2 tag RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRWD ERRWD: Error on L2 data RAM, Write Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRWT ERRWT: Error on L2 tag RAM, Write Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. PARRD PARRD: Parity Error on L2 data RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. PARRT PARRT: Parity Error on L2 tag RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ECNTR ECNTR: Event Counter1 and Event Counter 0 Overflow Increment Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. reg2_int_raw_status 3.3.9 Interrupt registers - Raw Interrupt Status Register The reg2_int_raw_status Register characteristics are: Purpose The Raw Interrupt Status Register enables the interrupt status that excludes the masking logic. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RO DECERR DECERR: DECERR from L3 Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. SLVERR SLVERR: SLVERR from L3 Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. ERRRD ERRRD: Error on L2 data RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. ERRRT ERRRT: Error on L2 tag RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. ERRWD ERRWD: Error on L2 data RAM, Write Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. ERRWT ERRWT: Error on L2 tag RAM, Write Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. PARRD PARRD: Parity Error on L2 data RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. PARRT PARRT: Parity Error on L2 tag RAM, Read Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. ECNTR ECNTR: Event Counter1 and Event Counter 0 Overflow Increment Bits read can be HIGH or LOW: HIGH = If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW = If the bits read LOW, no interrupt has been generated. reg2_int_clear 3.3.9 Interrupt registers - Interrupt Clear Register The reg2_int_clear Register characteristics are: Purpose Clears the Raw Interrupt Status Register bits. Usage constraints Non-secure access to this register is dependent on Auxiliary Control Register bit [27]. If bit [27] of the Auxiliary Control Register is set to 0, a Non secure write to this register results in a DECERR response. A read to this register returns zero. Configurations Available in all configurations. Attributes WO DECERR DECERR: DECERR from L3 When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. SLVERR SLVERR: SLVERR from L3 When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRRD ERRRD: Error on L2 data RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRRT ERRRT: Error on L2 tag RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRWD ERRWD: Error on L2 data RAM, Write When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRWT ERRWT: Error on L2 tag RAM, Write When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. PARRD PARRD: Parity Error on L2 data RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. PARRT PARRT: Parity Error on L2 tag RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ECNTR ECNTR: Event Counter1 and Event Counter 0 Overflow Increment When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. reg7_cache_sync 3.3.10 Cache Maintenance Operations - Cache Sync The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty. Attributes RW C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_inv_pa 3.3.10 Cache Maintenance Operations - Invalidate Line by PA The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Specific L2 cache line is marked as not valid. Attributes RW Tag_and_Index The bit position of the boundary between the Tag field and the Index field varies according to the Index bit width. C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_inv_way 3.3.10 Cache Maintenance Operations - Invalidate by Way The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Invalidate all data in specified ways, including dirty data. An Invalidate by way while selecting all cache ways is equivalent to invalidating all cache entries. Completes as a background task with the way, or ways, locked, preventing allocation. Attributes RW Way_bits For a 16-way implementation, all bits [15:0] are used. If the 16-way option is not enabled, bits [15:8] are reserved. reg7_clean_pa 3.3.10 Cache Maintenance Operations - Clean Line by PA The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged. Attributes RW Tag_and_Index The bit position of the boundary between the Tag field and the Index field varies according to the Index bit width. C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_clean_index 3.3.10 Cache Maintenance Operations - Clean Line by Set/Way The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid bit is unchanged. Attributes RW Way_and_Index The bit position of the boundary between the SBZ field and the Index field varies according to the Index bit width. For a 16-way implementation, all four bits [31:28] are used. If the 16-way option is not enabled, bit [31] is reserved. C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_clean_way 3.3.10 Cache Maintenance Operations - Clean by Way The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not dirty. The valid bits are unchanged. Completes as a background task with the way, or ways, locked, preventing allocation. Attributes RW Way_bits For a 16-way implementation, all bits [15:0] are used. If the 16-way option is not enabled, bits [15:8] are reserved. reg7_clean_inv_pa 3.3.10 Cache Maintenance Operations - Clean and Invalidate Line by PA The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid. Attributes RW Tag_and_Index The bit position of the boundary between the Tag field and the Index field varies according to the Index bit width. C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_clean_inv_index 3.3.10 Cache Maintenance Operations - Clean and Invalidate Line by Set/Way The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Write the specific L2 cache line within the specified way to L3 main memory if the line is marked as valid and dirty. The line is marked as not valid. Attributes RW Way_and_Index The bit position of the boundary between the SBZ field and the Index field varies according to the Index bit width. For a 16-way implementation, all four bits [31:28] are used. If the 16-way option is not enabled, bit [31] is reserved. C This operation stall the slave ports until they are complete. When this register is read, bit [0], the C flag, indicates that a background operation is in progress. When written, bit 0 must be zero. reg7_clean_inv_way 3.3.10 Cache Maintenance Operations - Clean and Invalidate by Way The Cache Maintenance Operations registers have different behavior, depending on the AXI security flag of the access requesting a cache operation. To perform the maintenance operation, perform a write to the corresponding register. If the operation is specific to the Way or Set/Way, their behavior is presented in the following manner: Secure access The secure bit of the tag is ignored and the maintenance operation can affect both secure and non-secure lines. Non-secure access The secure bit of the tag is checked, a lookup must be done for each non-secure maintenance operation, and the maintenance operation can only affect non-secure lines. Secure lines in cache are ignored and unmodified. Also, depending on the AXI security flag of the access requesting a cache operation, if the operation is specific to the Physical Address (PA), the behavior is presented in the following manner: Secure access The data in the cache is only affected by the operation if it is secure. Non-secure access The data in the cache is only affected by the operation if it is non-secure. Operation Writes each line of the specified L2 cache ways to L3 main memory if the line is marked as valid and dirty. The lines are marked as not valid. Completes as a background task with the way, or ways, locked, preventing allocation. Attributes RW Way_bits For a 16-way implementation, all bits [15:0] are used. If the 16-way option is not enabled, bits [15:8] are reserved. reg9_d_lockdown0 3.3.11 Cache lockdown - Data Lockdown 0 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK000 Use when AyUSERSx[7:5] = 0b000 reg9_i_lockdown0 3.3.11 Cache lockdown - Instruction Lockdown 0 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK000 Use when AyUSERSx[7:5] = 0b000 reg9_d_lockdown1 3.3.11 Cache lockdown - Data Lockdown 1 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK001 Use when AyUSERSx[7:5] = 0b001 reg9_i_lockdown1 3.3.11 Cache lockdown - Instruction Lockdown 1 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK001 Use when AyUSERSx[7:5] = 0b001 reg9_d_lockdown2 3.3.11 Cache lockdown - Data Lockdown 2 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK010 Use when AyUSERSx[7:5] = 0b010 reg9_i_lockdown2 3.3.11 Cache lockdown - Instruction Lockdown 2 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK010 Use when AyUSERSx[7:5] = 0b010 reg9_d_lockdown3 3.3.11 Cache lockdown - Data Lockdown 3 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK011 Use when AyUSERSx[7:5] = 0b011 reg9_i_lockdown3 3.3.11 Cache lockdown - Instruction Lockdown 3 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK011 Use when AyUSERSx[7:5] = 0b011 reg9_d_lockdown4 3.3.11 Cache lockdown - Data Lockdown 4 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK100 Use when AyUSERSx[7:5] = 0b100 reg9_i_lockdown4 3.3.11 Cache lockdown - Instruction Lockdown 4 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK100 Use when AyUSERSx[7:5] = 0b100 reg9_d_lockdown5 3.3.11 Cache lockdown - Data Lockdown 5 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK101 Use when AyUSERSx[7:5] = 0b101 reg9_i_lockdown5 3.3.11 Cache lockdown - Instruction Lockdown 5 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK101 Use when AyUSERSx[7:5] = 0b101 reg9_d_lockdown6 3.3.11 Cache lockdown - Data Lockdown 6 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK110 Use when AyUSERSx[7:5] = 0b110 reg9_i_lockdown6 3.3.11 Cache lockdown - Instruction Lockdown 6 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK110 Use when AyUSERSx[7:5] = 0b110 reg9_d_lockdown7 3.3.11 Cache lockdown - Data Lockdown 7 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW DATALOCK111 Use when AyUSERSx[7:5] = 0b111 reg9_i_lockdown7 3.3.11 Cache lockdown - Instruction Lockdown 7 Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW INSTRLOCK111 Use when AyUSERSx[7:5] = 0b111 reg9_lock_line_en 3.3.11 Cache lockdown - Lockdown by Line Enable Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW lockdown_by_line_enable 0 = Lockdown by line disabled. This is the default. 1 = Lockdown by line enabled. reg9_unlock_way 3.3.11 Cache lockdown - Unlock All Lines Register These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions. Attributes RW unlock_all_lines_by_way_ope For all bits: 0 = Unlock all lines disabled. This is the default. 1 = Unlock all lines operation in progress for the corresponding way. reg12_addr_filtering_start 3.3.12 Address filtering - Address Filtering Start Register When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and < address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers. Attributes RW address_filtering_start Address filtering start address for bits [31:20] of the filtering address. address_filtering_enable 0 = address filtering disabled 1 = address filtering enabled. reg12_addr_filtering_end 3.3.12 Address filtering - Address Filtering End Register When two masters are implemented, you can redirect a whole address range to master 1 (M1). When address_filtering_enable is set, all accesses with address >= address_filtering_start and < address_filtering_end are automatically directed to M1. All other accesses are directed to M0. This feature is programmed using two registers. Attributes RW address_filtering_end Address filtering end address for bits [31:20] of the filtering address. reg15_debug_ctrl 3.3.13 Debug Register The Debug Control Register forces specific cache behavior required for debug. This register has read-only, non-secure, or read and write, secure, permission. Any secure access and non-secure access can read this register. Only a secure access can write to this register. If a non-secure access tries to write to this register the register issues a DECERR response and does not update. Attributes RW SPNIDEN Reads value of SPNIDEN input. DWB DWB: Disable write-back, force WT 0 = Enable write-back behavior. This is the default. 1 = Force write-through behavior. DCL DCL: Disable cache linefill 0 = Enable cache linefills. This is the default. 1 = Disable cache linefills. reg15_prefetch_ctrl 3.3.14 Prefetch Control Register The Prefetch Control Register characteristics are: Purpose Enables prefetch-related features that can improve system performance. Usage constraints This register has both read-only, non-secure, and read and write, secure, permissions. Any secure or non-secure access can read this register. Only a secure access can write to this register. If a non-secure access attempts to write to this register, the register issues a DECERR response and does not update. ---- Note ---- You must preserve the reserved bits when you write to this register. -------------- Configurations Available in all configurations. Attributes RW Double_linefill_enable You can set the following options for this register bit: 0 = The L2CC always issues 4x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default. 1 = The L2CC issues 8x64-bit read bursts to L3 on reads that miss in the L2 cache. Instruction_prefetch_enable You can set the following options for this register bit: 0 = Instruction prefetching disabled. This is the default. 1 = Instruction prefetching enabled. Data_prefetch_enable You can set the following options for this register bit: 0 = Data prefetching disabled. This is the default. 1 = Data prefetching enabled. DoubleLF_on_WRAPread_dis You can set the following options for this register bit: 0 = Double linefill on WRAP read enabled. This is the default. 1 = Double linefill on WRAP read disabled. Prefetch_drop_enable You can set the following options for this register bit: 0 = The L2CC does not discard prefetch reads issued to L3. This is the default. 1 = The L2CC discards prefetch reads issued to L3 when there is a resource conflict with explicit reads. Incr_DoubleLF_enable You can set the following options for this register bit: 0 = The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default. 1 = The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. NOTsameID_on_exclusive_seq_en You can set the following options for this register bit: 0 = Read and write portions of a non-cacheable exclusive sequence have the same AXI ID when issued to L3. This is the default. 1 = Read and write portions of a non-cacheable exclusive sequence do not have the same AXI ID when issued to L3. Prefetch_offset Default value = 0b00000. ---- Note ---- You must only use the Prefetch offset values of 0-7, 15, 23, and 31 for these bits. The L2C-310 does not support the other values. reg15_power_ctrl 3.3.15 Power Control Register The pwr_ctrl Register characteristics are: Purpose Controls the operating mode clock and power modes. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes RW dynamic_clk_gating_en Dynamic clock gating enable. 0 = Disabled. This is the default. 1 = Enabled. standby_mode_en Standby mode enable. 0 = Disabled. This is the default. 1 = Enabled.