default_vendor_com addon ARM IP registers. Address map for the HHP HPS system-domain mpuscu This address space is allocated to the MPU. For detailed information about the use of this address space, [url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/index.html]click here[/url] to access the ARM documentation for the Cortex-A9 MPCore. offset=0x0000~: This address space is allocated for the Snoop Control Unit registers. offset=0x0100~: This address space is allocated for cpu interface registers of the General Interrupt Controller (GIC). offset=0x0200~: This address space is allocated for the Global Timer registers. offset=0x0600~: This is the address space is allocated for private timers and watchdog timers. offset=0x1000~: This address space is allocated for interrupt distributor registers of the General Interrupt Controller (GIC). scu_control 2.2.1 SCU Control Register The SCU Control Register characteristics are: Purpose • enables speculative linefills to L2 with L2C-310 • enables Force all Device to port0 • enables IC standby mode • enables SCU standby mode • enables SCU RAM parity support • enables address filtering • enables the SCU. Usage constraints • This register is writable in Secure state if the relevant bit in the SAC register is set. • This register is writable in Non-secure state if the relevant bits in the SAC and SNSAC registers are set. Configurations Available in all Cortex-A9 multiprocessor configurations. Attributes Secure accress:RW / Non-secure access:RW IC_standby_enable When set, this stops the Interrupt Controller clock when no interrupts are pending, and no CPU is performing a read/write request. This bit is set to 0 by default SCU_standby_enable When set, SCU CLK is turned off when all processors are in WFI mode, there is no pending request on the ACP, if implemented, and there is no remaining activity in the SCU. When SCU CLK is off, ARREADYS, AWREADYS and WREADYS on the ACP are forced LOW. The clock is turned on when any processor leaves WFI mode, or if there is a new request on the ACP. This bit is set to 0 by default Force_all_Device_to_port0_enable When set, all requests from the ACP or processors with AxCACHE = Noncacheable Bufferable are forced to be issued on the AXI Master port M0. See Address filtering capabilities on page 2-17. This bit is set to 0 by default SCU_Speculative_linefills_enable When set, coherent linefill requests are sent speculatively to the L2C-310 in parallel with the tag look-up. If the tag look-up misses, the confirmed linefill is sent to the L2C-310 and gets RDATA earlier because the data request was already initiated by the speculative request. This feature works only if the L2C-310 is present in the design. This bit is set to 0 by default SCU_RAMs_Parity_enable 0 = Parity off. This is the default setting. 1 = Parity on. This bit is always zero if support for parity is not implemented. Address_filtering_enable 0 = Addressing filtering off. 1 = Addressing filtering on. The default value is the value of FILTEREN sampled when nSCURESET is deasserted. This bit is always zero if the SCU is implemented in the single master port configuration. See Address filtering capabilities on page 2-17. SCU_enable 0 = SCU enable. 1 = SCU disable. This is the default setting. scu_configuration 2.2.2 SCU Configuration Register The SCU Configuration Register characteristics are: Purpose • read tag RAM sizes for the Cortex-A9 processors that are present • determine the Cortex-A9 processors that are taking part in coherency • read the number of Cortex-A9 processors present. Usage constraints This register is read-only. Configurations Available in all Cortex-A9 multiprocessor configurations. Attributes Secure accress:RO / Non-secure access:RO Tag_RAM_sizes Bits [15:14] indicate Cortex-A9 processor CPU3 tag RAM size if present. Bits [13:12] indicate Cortex-A9 processor CPU2 tag RAM size if present. Bits [11:10] indicate Cortex-A9 processor CPU1 tag RAM size if present. Bits [9:8] indicate Cortex-A9 processor CPU0 tag RAM size. The encoding is as follows: b00 = 16KB cache, 64 indexes per tag RAM. b01 = 32KB cache, 128 indexes per tag RAM. b10 = 64KB cache, 256 indexes per tag RAM. b11 = Reserved Non-present CPUs have a Tag RAM size of b00, the same as 16KB. CPUs_SMP Shows the Cortex-A9 processors that are in Symmetric Multi-processing (SMP) or Asymmetric Multi-processing (AMP) mode. 0 = This Cortex-A9 processor is in AMP mode, not taking part in coherency, or not present. 1 = This Cortex-A9 processor is in SMP mode, taking part in coherency. Bit 7 is for CPU3 Bit 6 is for CPU2 Bit 5 is for CPU1 Bit 4 is for CPU0. CPU_number Number of CPUs present in the Cortex-A9 MPCore processor b00 = One Cortex-A9 processor, CPU0. b01 = Two Cortex-A9 processors, CPU0 and CPU1. b10 = Three Cortex-A9 processors, CPU0, CPU1, and CPU2. b11 = Four Cortex-A9 processors, CPU0, CPU1, CPU2, and CPU3. scu_cpupower_status 2.2.3 SCU CPU Power Status Register The SCU CPU Power Status Register characteristics are: Purpose Specifies the state of the Cortex-A9 processors with reference to power modes Usage constraints This register is writable in Secure state if the relevant bit in the SAC register is set. This register is writable in Non-secure state if the relevant bits in the SAC and SNSAC registers are set. Dormant mode and powered-off mode are controlled by an external power controller. SCU CPU Status Register bits indicate to the external power controller the power domains that can be powered down. Before entering any other power mode than Normal, the Cortex-A9 processor must set its status field to signal to the power controller the mode it is about to enter. The Cortex-A9 processor then executes a WFI entry instruction. When in WFI state, the PWRCTLOn bus is enabled and signals to the power controller what it must do with power domains. The SCU CPU Power Status Register bits can also be read by a Cortex-A9 processor exiting low-power mode to determine its state before executing its reset setup. Cortex-A9 processors status fields take PWRCTLIn values at reset, except for nonpresent Cortex-A9 processors. For nonpresent Cortex-A9 processors writing to this field has no effect. Configurations Available in all Cortex-A9 MPCore configurations. Attributes Secure accress:RW / Non-secure access:RW CPU3_status Power status of the Cortex-A9 processor: b00 = Normal mode. b01 = Reserved. b10 = The Cortex-A9 processor is about to enter, or is in, dormant mode. No coherency request is sent to the Cortex-A9 processor. b11 = The Cortex-A9 processor is about to enter, or is in, powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor. The default value is b00 when CPU3 processor is present, else b11 CPU2_status Power status of the Cortex-A9 processor: b00 = Normal mode. b01 = Reserved. b10 = The Cortex-A9 processor is about to enter, or is in, dormant mode. No coherency request is sent to the Cortex-A9 processor. b11 = The Cortex-A9 processor is about to enter, or is in, powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor. The default value is b00 when CPU2 processor is present, else b11 CPU1_status Power status of the Cortex-A9 processor: b00 = Normal mode. b01 = Reserved. b10 = The Cortex-A9 processor is about to enter, or is in, dormant mode. No coherency request is sent to the Cortex-A9 processor. b11 = The Cortex-A9 processor is about to enter, or is in, powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor. The default value is b00 when CPU1 processor is present, else b11 CPU0_status Power status of the Cortex-A9 processor: b00 = Normal mode. b01 = Reserved. b10 = The Cortex-A9 processor is about to enter, or is in, dormant mode. No coherency request is sent to the Cortex-A9 processor. b11 = The Cortex-A9 processor is about to enter, or is in, powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor. The default value is b00 when CPU0 processor is present, else b11 scu_invalidateall_secure 2.2.4 SCU Invalidate All Registers in Secure State Register The SCU Invalidate All Registers in Secure State characteristics are: Purpose Invalidates the SCU tag RAMs on a per Cortex-A9 processor and per way basis. Usage constraints This register: • Invalidates all lines in the selected ways. • Is a write-only register that always reads as zero. Configurations Available in all Cortex-A9 multiprocessor configurations. Attributes Secure accress:WO / Non-secure access:- CPU3_ways Specifies the ways that must be invalidated for CPU3. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than four processors. CPU2_ways Specifies the ways that must be invalidated for CPU2. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than three processors. CPU1_ways Specifies the ways that must be invalidated for CPU1. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than two processors. CPU0_ways Specifies the ways that must be invalidated for CPU0. scu_filtering_start 2.2.5 Filtering Start Address Register The Filtering Start Address Register characteristics are: Purpose Provides the start address for use with master port 1 in a two-master port configuration. Usage constraints This register is writable: • in Secure state if the relevant bit in the SAC register is set. • in Non-secure state if the relevant bits in the SAC and SNSAC registers are set. Configurations Available in all two-master port configurations. When only one master port is present these registers are not implemented. Writes have no effect and reads return a value 0x0 for all filtering registers. Attributes Secure accress:RW / Non-secure access:RW Filtering_start_address Start address for use with master port 1 in a two-master port configuration when address filtering is enabled. The default value is the value of FILTERSTART sampled on exit from reset. The value on the pin gives the upper address bits with 1MB granularity. scu_filtering_end 2.2.6 Filtering End Address Register The Filtering End Address Register characteristics are: Purpose Provides the end address for use with master port 1 in a two-master port configuration. Usage constraints This register is writable • in Secure state if the relevant bit in the SAC register is set. • in Non-secure state if the relevant bits in the SAC and SNSAC registers are set. • has an inclusive address as its end address. This means that the topmost megabyte of address space of memory can be included in the filtering address range. Configurations Available in all two-master product configurations. When only one master port is present writes have no effect and reads return a value 0x0 for all filtering registers. Attributes Secure accress:RW / Non-secure access:RW Filtering_end_address End address for use with master port 1 in a two-master port configuration, when address filtering is enabled. The default value is the value of FILTEREND sampled on exit from reset. The value on the pin gives the upper address bits with 1MB granularity. scu_access_control 2.2.7 SCU Access Control Register (SAC) The SAC characteristics are: Purpose Controls access to the following registers on a per Cortex-A9 processor basis: • SCU Control Register on page 2-3 • SCU CPU Power Status Register on page 2-6 • SCU Invalidate All Registers in Secure State Register on page 2-7 • Filtering Start Address Register on page 2-8 • Filtering End Address Register on page 2-9 • SCU Non-secure Access Control Register on page 2-11. A processor in the Cortex-A9 MPCore multiprocessor can set up the SCU and then write zero to the register. This prevents any Secure or Non-secure access from altering the configuration of the register again. This prevents any more changes to the SCU configuration after booting. Usage constraints This register is writable: • in Secure state if the relevant bit in the SAC register is set. • in Non-secure state if the relevant bits in the SAC and SNSAC are set. Configurations Available in all Cortex-A9 MPCore configurations. Attributes Secure accress:RW / Non-secure access:RW CPU3 0 = CPU3 cannot access the registers. 1 = CPU3 can access the registers. This is the default. CPU2 0 = CPU2 cannot access the registers. 1 = CPU2 can access the registers. This is the default. CPU1 0 = CPU1 cannot access the registers. 1 = CPU1 can access the registers. This is the default. CPU0 0 = CPU0 cannot access the registers. 1 = CPU0 can access the registers. This is the default. scu_nonsecure_access_control 2.2.8 SCU Non-secure Access Control Register The SNSAC register characteristics are: Purpose Controls Non-secure access to the following registers on a per Cortex-A9 processor basis: • SCU Control Register on page 2-3 • SCU CPU Power Status Register on page 2-6 • Filtering Start Address Register on page 2-8 • Filtering End Address Register on page 2-9 • SCU Access Control Register (SAC) on page 2-10. In addition it controls Non-secure access to the global timer, private timers, and watchdog. Usage constraints • This register is writable in Secure state if the relevant bit in the SAC register is set. Configurations Available in all Cortex-A9 multiprocessor configurations. Attributes Secure accress:RW / Non-secure access:RO CPU3_global_timer Non-secure access to the global timer for CPU3. 0 = Secure accesses only. This is the default value. 1 = Secure accesses and Non-Secure accesses. CPU2_global_timer Non-secure access to the global timer for CPU2. 0 = Secure accesses only. This is the default value. 1 = Secure accesses and Non-Secure accesses. CPU1_global_timer Non-secure access to the global timer for CPU1. 0 = Secure accesses only. This is the default value. 1 = Secure accesses and Non-Secure accesses. CPU0_global_timer Non-secure access to the global timer for CPU0. 0 = Secure accesses only. This is the default value. 1 = Secure accesses and Non-Secure accesses. Private_timer_for_CPU3 Non-secure access to the private timer and watchdog for CPU3. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses. Private_timer_for_CPU2 Non-secure access to the private timer and watchdog for CPU2. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses. Private_timer_for_CPU1 Non-secure access to the private timer and watchdog for CPU1. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses. Private_timer_for_CPU0 Non-secure access to the private timer and watchdog for CPU0. 0 = Secure accesses only. Non-secure reads return 0. This is the default value. 1 = Secure accesses and Non-secure accesses. Register_access_for_CPU3 Non-secure access to the registers for CPU3. 0 = CPU cannot write the registers. 1 = CPU can access the registers. Register_access_for_CPU2 Non-secure access to the registers for CPU2. 0 = CPU cannot write the registers. 1 = CPU can access the registers. Register_access_for_CPU1 Non-secure access to the registers for CPU1. 0 = CPU cannot write the registers. 1 = CPU can access the registers. Register_access_for_CPU0 Non-secure access to the registers for CPU0. 0 = CPU cannot write the registers. 1 = CPU can access the registers. ICCICR 4.4.1 CPU Interface Control Register, GICC_CTLR The GICC_CTLR characteristics are: Purpose Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. Usage constraints If the GIC implements the Security Extensions with support for configuration lockdown, the system can prevent write access to certain register fields in the Secure GICC_CTLR, see Configuration lockdown on page 4-82. Configurations If the implementation supports interrupt grouping, this register provides independent control of Group 0 and Group 1 interrupts. If the GIC implements the Security Extensions: * this register is banked to provide Secure and Non-secure copies, see Register banking on page 4-77 * the register bit assignments are different in the Secure and Non-secure copies of the register, and: — the Secure copy of the register can control both Group 0 and Group 1 interrupts — the Non-secure copy of the register can control only Group 1 interrupts. Attributes RW Enable Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor. 0 = Disable signaling of interrupts 1 = Enable signaling of interrupts. -------- Note -------- * When this bit is cleared to 0, the CPU interface ignores any pending interrupt forwarded to it. When this bit is set to 1, the CPU interface starts to process pending interrupts that are forwarded to it. There is a small but finite time required for a change to take effect. * On a GICv1 implementation that does not include the Security Extensions, this bit controls the signaling of all interrupts by the CPU interface to the connected processor. ---------------------- See Enabling and disabling the Distributor and CPU interfaces on page 4-77 for more information about this bit. ICCPMR 4.4.2 Interrupt Priority Mask Register, GICC_PMR The GICC_PMR characteristics are: Purpose Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register are signaled to the processor. -------- Note -------- Higher priority corresponds to a lower Priority field value. ---------------------- Usage constraints If the GIC implements the Security Extensions then: * a Non-secure access to this register can only read or write a value that corresponds to the lower half of the priority range, see Interrupt grouping and interrupt prioritization on page 3-53. * if a Secure write has programmed the GICC_PMR with a value that corresponds to a value in the upper half of the priority range then: — any Non-secure read of the GICC_PMR returns 0x00, regardless of the value held in the register — any Non-secure write to the GICC_PMR is ignored. For more information see Non-secure access to register fields for Group 0 interrupt priorities on page 4-81. When determining interrupt preemption, the priority value can be split into two parts, using the Binary Point register, GICC_BPR. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions, this register is Common. Attributes RW Priority The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor. If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows: 128 supported levels Bit [0] = 0. 64 supported levels Bit [1:0] = 0b00. 32 supported levels Bit [2:0] = 0b000. 16 supported levels Bit [3:0] = 0b0000. For more information see Interrupt prioritization on page 3-44. ICCBPR 4.4.3 Binary Point Register, GICC_BPR The GICC_BPR characteristics are: Purpose The register defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field is used to determine interrupt preemption. Usage constraints The minimum binary point value is IMPLEMENTATION DEFINED in the range: * 0-3 if the implementation does not include the GIC Security Extensions, and for the Secure copy of the register if the implementation includes the Security Extensions * 1-4 for the Non-secure copy of the register. An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. On a reset, the binary point field is set to the minimum supported value. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions: * this register is banked to provide Secure and Non-secure copies, see Register banking on page 4-77 * the GICC_ABPR is an alias of the Non-secure copy of GICC_BPR * the GICC_CTLR.CBPR bit affects the view of the Non-secure GICC_BPR. In any GICv2 implementation, or in a GICv1 implementation that includes the Security Extensions, GICC_CTLR.CBPR controls whether the Secure copy of the GICC_BPR, or the GICC_ABPR, is used for the preemption of Group 1 interrupts. Attributes RW Binary_point The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field. For how this field determines the interrupt priority bits assigned to the group priority field see: * Table 3-7 on page 3-57, for the processing of Group 1 interrupts on a GIC that supports interrupt grouping, when the GICC_CTLR.CBPR bit is set to 1 * Table 3-2 on page 3-46, for all other cases. See Priority grouping on page 3-45 for more information. ICCIAR 4.4.4 Interrupt Acknowledge Register, GICC_IAR The GICC_IAR characteristics are: Purpose The processor reads this register to obtain the interrupt ID of the signaled interrupt. This read acts as an acknowledge for the interrupt. Usage constraints When GICC_CTLR.AckCtl is set to 0 in a GICv2 implementation that does not include the Security Extensions, if the highest priority pending interrupt is in Group 1, the interrupt ID 1022 is returned. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions: * this register is Common. * the GICC_AIAR is an alias of the Non-secure view of this register. Attributes RO CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. Interrupt_ID The interrupt ID. ICCEOIR 4.4.5 End of Interrupt Register, GICC_EOIR The GICC_EOIR characteristics are: Purpose A processor writes to this register to inform the CPU interface either: * that it has completed the processing of the specified interrupt * in a GICv2 implementation, when the appropriate GICC_CTLR.EOImode bit is set to 1, to indicate that the interface should perform priority drop for the specified interrupt. See Priority drop and interrupt deactivation on page 3-38 for more information. Usage constraints A write to this register must correspond to the most recent valid read from an Interrupt Acknowledge Register. A valid read is a read that returns a valid interrupt ID, that is not a spurious interrupt ID. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes WO CPUID On a multiprocessor implementation, if the write refers to an SGI, this field contains the CPUID value from the corresponding GICC_IAR access. In all other cases this field SBZ. EOIINTID The Interrupt ID value from the corresponding GICC_IAR access. ICCRPR 4.4.6 Running Priority Register, GICC_RPR The GICC_RPR characteristics are: Purpose Indicates the Running priority of the CPU interface. Usage constraints If there is no active interrupt on the CPU interface, the value returned is the Idle priority. -------- Note -------- Software cannot determine the number of implemented priority bits from a read of this register. ---------------------- If the GIC implements the Security Extensions, the value returned by a Non-secure read of the Priority field is: * 0x00 if the field value is less than 0x80 * the Non-secure view of the Priority value if the field value is 0x80 or more. For more information see Non-secure access to register fields for Group 0 interrupt priorities on page 4-81. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes RO Priority The current running priority on the CPU interface. ICCHPIR 4.4.7 Highest Priority Pending Interrupt Register, GICC_HPPIR The GICC_HPPIR characteristics are: Purpose Indicates the Interrupt ID, and processor ID if appropriate, of the highest priority pending interrupt on the CPU interface. Usage constraints Never returns the Interrupt ID of an interrupt that is active and pending. Returns a processor ID only for an SGI in a multiprocessor implementation. If the GIC supports interrupt grouping, the value returned by a read of GICC_HPPIR can depend on: * the value of GICC_CTLR.AckCtl * if the GIC implements the Security Extensions, whether the register access is Secure or Non-secure: See Effect of interrupt grouping and the Security Extensions on reads of the GICC_HPPIR. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes RO CPUID On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. In all other cases this field is RAZ. PENDINTID The interrupt ID of the highest priority pending interrupt. See Table 4-42 on page 4-144 for more information about the result of Non-secure reads of the GICC_HPPIR when the GIC implements the Security Extensions. ICCABPR 4.4.8 Aliased Binary Point Register, GICC_ABPR The GICC_ABPR characteristics are: Purpose A Binary Point Register for handling Group 1 interrupts. The reset value of this register is defined as (minimum GICC_BPR.Binary point + 1), resulting in a permitted range of 0x1-0x4. Usage constraints If the GIC implements the Security Extensions, accessible by Secure accesses only. Configurations This register is present only in GICv2, and in GICv1 implementations that include the Security Extensions, In a GIC implementation that includes the Security Extensions, GICC_ABPR is an alias of the Non-secure GICC_BPR, and when GICC_CTLR.CBPR is set to 0, a Secure access to this register is equivalent to a Non-secure access to GICC_IAR. -------- Note -------- * GICC_ABPR is redundant when GICC_CTLR.CBPR is set to 1. In a GIC implementation that includes the Security Extensions, when GICC_CTLR.CBPR is set to 1, the behavior of Secure accesses to GICC_ABPR is not identical to the behavior of Non-secure accesses to GICC_BPR * Accesses to the GICC_ABPR are unaffected by the value of the GICC_CTLR.CBPR bit. ---------------------- If the GIC implementation includes the Security Extensions, GICC_ABPR is a Secure register. If the GIC does not implement the GICC_ABPR, the address is RAZ/WI. Attributes RW Binary_point The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field. For how this field determines the interrupt priority bits assigned to the group priority field see: * Table 3-7 on page 3-57, for the processing of Group 1 interrupts on a GIC that supports interrupt grouping, when the GICC_CTLR.CBPR bit is set to 1 * Table 3-2 on page 3-46, for all other cases. See Priority grouping on page 3-45 for more information. ICCIDR 4.4.14 CPU Interface Identification Register, GICC_IIDR The GICC_IIDR characteristics are: Purpose Provides information about the implementer and revision of the CPU interface. Usage constraints No usage constraints. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes RO ProductID An IMPLEMENTATION DEFINED product identifier. Architecture_version The value of this field depends on the GIC architecture version, as follows: 0x1 = for GICv1 0x2 = for GICv2. Revision An IMPLEMENTATION DEFINED revision number for the CPU interface. Implementer Contains the JEP106 code of the company that implemented the GIC CPU interface: Bits[11:8] The JEP106 continuation code of the implementer. Bit[7] Always 0. Bits[6:0] The JEP106 identity code of the implementer. privatetimer_load 4.2.1 Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register. Attributes RW privatetimer_counter 4.2.2 Private Timer Counter Register The Timer Counter Register is a decrementing counter. The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register. If a Cortex-A9 processor timer is in debug state, the counter only decrements when the Cortex-A9 processor returns to non debug state. When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops. When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register. Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value. Attributes RW privatetimer_control 4.2.3 Private Timer Control Register Attributes RW Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals on page 4-2 for the equation. IRQ_enable If set, the interrupt ID 29 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. Auto_reload 0 = Single shot mode. Counter decrements down to zero, sets the event flag and stops. 1 = Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. Timer_Enable Timer enable: 0 = Timer is disabled and the counter does not decrement. All registers can still be read and written 1 = Timer is enabled and the counter decrements normally. privatetimer_interrupt_status 4.2.4 Private Timer Interrupt Status Register This is a banked register for all Cortex-A9 processors present. The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. Attributes RW Event_flag watchdog_load 4.2.5 Watchdog Load Register The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register. Attributes RW watchdog_counter 4.2.6 Watchdog Counter Register The Watchdog Counter Register is a down counter. It decrements if the Watchdog is enabled using the Watchdog enable bit in the Watchdog Control Register. If the Cortex-A9 processor associated with the Watchdog is in debug state, the counter does not decrement until the Cortex-A9 processor returns to non debug state. When the Watchdog Counter Register reaches zero and auto reload mode is enabled, and in timer mode, it reloads the value in the Watchdog Load Register and then decrements from that value. If auto reload mode is not enabled or the watchdog is not in timer mode, the Watchdog Counter Register decrements down to zero and stops. When in watchdog mode the only way to update the Watchdog Counter Register is to write to the Watchdog Load Register. When in timer mode the Watchdog Counter Register is write accessible. The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its mode: - Timer mode When the Watchdog Counter Register reaches zero, the watchdog interrupt status event flag is set and the interrupt ID 30 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Watchdog Control Register. - Watchdog mode If a software failure prevents the Watchdog Counter Register from being refreshed, the Watchdog Counter Register reaches zero, the Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted for one PERIPHCLK cycle. The external reset source is then responsible for resetting all or part of the Cortex-A9 MPCore design. Attributes RW watchdog_control 4.2.7 Watchdog Control Register Attributes RW Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals on page 4-2. Watchdog_mode 0 = Timer mode, default. Writing a zero to this bit has no effect. You must use the Watchdog Disable Register to put the watchdog into timer mode. See Watchdog Disable Register on page 4-7. 1 = Watchdog mode. IT_Enable If set, the interrupt ID 30 is set as pending in the Interrupt Distributor when the event flag is set in the watchdog Status Register. In watchdog mode this bit is ignored. Auto_reload 0 = Single shot mode. Counter decrements down to zero, sets the event flag and stops. 1 = Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Load Register and then continues decrementing. Watchdog_Enable Global watchdog enable 0 = Watchdog is disabled and the counter does not decrement. All registers can still be read and /or written. 1 = Watchdog is enabled and the counter decrements normally. watchdog_interrupt_status 4.2.8 Watchdog Interrupt Status Register The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. If the watchdog interrupt is enabled, Interrupt ID 30 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written with a value of 1. Trying to write a zero to the event flag or a one when it is not set has no effect. Attributes RW Event_flag watchdog_reset_status 4.2.9 Watchdog Reset Status Register The reset flag is a sticky bit that is automatically set, in watchdog mode, when the Counter Register reaches zero and a reset request is sent accordingly. The reset flag is cleared when written with a value of 1. Trying to write a zero to the reset flag or a one when it is not set has no effect. This flag is not reset by normal Cortex-A9 processor resets but has its own reset line, nWDRESET. nWDRESET must not be asserted when the Cortex-A9 processor reset assertion is the result of a watchdog reset request with WDRESETREQ. This distinction enables software to differentiate between a normal boot sequence, reset flag is zero, and one caused by a previous watchdog time-out, reset flag set to one. Attributes RW Reset_flag watchdog_disable 4.2.10 Watchdog Disable Register Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero. If one of the values written to the Watchdog Disable Register is incorrect or if any other write occurs in between the two word writes, the watchdog remains in the same mode. To reactivate the Watchdog, the software must write 1 to the watchdog mode bit of the Watchdog Control Register. See Watchdog Control Register on page 4-5. Attributes RO globaltimer_counter_lower32 4.4.1 Global Timer Counter Registers, 0x00 and 0x04 - Lower 32bit There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and the upper 32-bit timer counter at offset 0x04. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. To modify the register proceed as follows: 1. Clear the timer enable bit in the Global Timer Control Register 2. Write the lower 32-bit timer counter register 3. Write the upper 32-bit timer counter register 4. Set the timer enable bit. To get the value from the Global Timer Counter register proceed as follows: 1. Read the upper 32-bit timer counter register 2. Read the lower 32-bit timer counter register 3. Read the upper 32-bit timer counter register again. If the value is different to the 32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer counter value is correct. Attributes RW globaltimer_counter_upper32 4.4.1 Global Timer Counter Registers, 0x00 and 0x04 - Upper 32bit There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and the upper 32-bit timer counter at offset 0x04. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. To modify the register proceed as follows: 1. Clear the timer enable bit in the Global Timer Control Register 2. Write the lower 32-bit timer counter register 3. Write the upper 32-bit timer counter register 4. Set the timer enable bit. To get the value from the Global Timer Counter register proceed as follows: 1. Read the upper 32-bit timer counter register 2. Read the lower 32-bit timer counter register 3. Read the upper 32-bit timer counter register again. If the value is different to the 32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer counter value is correct. Attributes RW globaltimer_control 4.4.2 Global Timer Control Register Attributes RW Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals on page 4-2 for the equation. Auto_increment This bit is banked per Cortex-A9 processor. 0 = Single shot mode. When the counter reaches the comparator value, sets the event flag. It is the responsibility of software to update the comparator value to get more events. 1 = Auto increment mode. Each time the counter reaches the comparator value, the comparator register is incremented with the auto-increment register, so that more events can be set periodically without any software updates. IRQ_Enable This bit is banked per Cortex-A9 processor. If set, the interrupt ID 27 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. Comp_Enable This bit is banked per Cortex-A9 processor. If set, it enables the comparison between the 64-bit Timer Counter and the related 64-bit Comparator Register. Timer_Enable Timer enable 0 = Timer is disabled and the counter does not increment. All registers can still be read and written. 1 = Timer is enabled and the counter increments normally. globaltimer_interrupt_status 4.4.3 Global Timer Interrupt Status Register This is a banked register for all Cortex-A9 processors present. The event flag is a sticky bit that is automatically set when the Counter Register reaches the Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. Figure 4-7 shows the Global Timer Interrupt Status Register bit assignment. Attributes RW Event_flag globaltimer_comparator_lower32 4.4.4 Comparator Value Registers, 0x10 and 0x14 - Lower 32bit There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10 and the upper 32-bit comparator value register at offset 0x14. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There is a Comparator Value Register for each Cortex-A9 processor. To ensure that updates to this register do not set the Interrupt Status Register proceed as follows: 1. Clear the Comp Enable bit in the Timer Control Register. 2. Write the lower 32-bit Comparator Value Register. 3. Write the upper 32-bit Comparator Value Register. 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. Attributes RW globaltimer_comparator_upper32 4.4.4 Comparator Value Registers, 0x10 and 0x14 - Upper 32bit There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10 and the upper 32-bit comparator value register at offset 0x14. You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There is a Comparator Value Register for each Cortex-A9 processor. To ensure that updates to this register do not set the Interrupt Status Register proceed as follows: 1. Clear the Comp Enable bit in the Timer Control Register. 2. Write the lower 32-bit Comparator Value Register. 3. Write the upper 32-bit Comparator Value Register. 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. Attributes RW globaltimer_autoincrement 4.4.5 Auto-increment Register, 0x18 This 32-bit register gives the increment value of the Comparator Register when the Auto-increment bit is set in the Timer Control Register. Each Cortex-A9 processor present has its own Auto-increment Register. If the comp enable and auto-increment bits are set when the global counter reaches the Comparator Register value, the comparator is incremented by the auto-increment value, so that a new event can be set periodically. The global timer is not affected and goes on incrementing. Attributes RW ICDDCR Distributor Control Register 4.3.1 Distributor Control Register, GICD_CTLR The GICD_CTLR characteristics are: Purpose Enables the forwarding of pending interrupts from the Distributor to the CPU interfaces. Usage constraints If the GIC implements the Security Extensions with configuration lockdown, the system can lock down the Secure GICD_CTLR, see Configuration lockdown on page 4-82. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions, this register is banked, see Register banking on page 4-77. Attributes RW ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.1 Distributor Control Register The ICDDCR characteristics are: Purpose Controls whether the distributor responds to external stimulus changes that occur on SPIs and PPIs. Usage constraints This register is banked. The register you access depends on the type of access: Secure access Distributor provides access to the Secure Enable and Non-Secure Enable bits. See Figure 3-1 on page 3-7. Non-secure access Distributor provides access to the Non-Secure enable bit only. See Figure 3-2 on page 3-7. You cannot modify Enable Secure if CFGSDISABLE is set. You can modify Enable Non-Secure even if CFGSDISABLE is set, through the S or the NS register. Configurations Available in all Cortex-A9 MPCore configurations. ICDICTR 4.3.2 Interrupt Controller Type Register, GICD_TYPER The GICD_TYPER characteristics are: Purpose Provides information about the configuration of the GIC. It indicates: * whether the GIC implements the Security Extensions * the maximum number of interrupt IDs that the GIC supports * the number of CPU interfaces implemented * if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). Usage constraints No usage constraints. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes RO ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.2 Interrupt Controller Type Register The ICDICTR characteristics are: Purpose Provides information about the configuration of the Interrupt Controller. Usage constraints There are no usage constraints. Configurations Available in all Cortex-A9 MPCore configurations. ICDIIDR 4.3.3 Distributor Implementer Identification Register, GICD_IIDR The GICD_IIDR characteristics are: Purpose Provides information about the implementer and revision of the Distributor. Usage constraints No usage constraints. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. Attributes RO ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.3 Distributor Implementer Identification Register The ICDIIDR characteristics are: Purpose Provides information about the implementer and the revision of the controller Usage constraints There are no usage constraints. Configurations Available in all Cortex-A9 MPCore configurations. ICDISR0 4.3.4 Interrupt Group Registers, GICD_IGROUPRn The GICD_IGROUPR characteristics are: Purpose The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC. Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. Usage constraints In implementations that include the GIC Security Extensions, accessible by Secure accesses only. The register addresses are RAZ/WI to Non-secure accesses. A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements configuration lockdown, the system can lockdown the group status bits for lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82. Attributes RW Security_status_sgi_0Security status. Security_status_sgi_1Security status. Security_status_sgi_2Security status. Security_status_sgi_3Security status. Security_status_sgi_4Security status. Security_status_sgi_5Security status. Security_status_sgi_6Security status. Security_status_sgi_7Security status. Security_status_sgi_8Security status. Security_status_sgi_9Security status. Security_status_sgi_10Security status. Security_status_sgi_11Security status. Security_status_sgi_12Security status. Security_status_sgi_13Security status. Security_status_sgi_14Security status. Security_status_sgi_15Security status. Security_status_ppi_0Security status. Security_status_ppi_1Security status. Security_status_ppi_2Security status. Security_status_ppi_3Security status. Security_status_ppi_4Security status. Security_status_ppi_5Security status. Security_status_ppi_6Security status. Security_status_ppi_7Security status. Security_status_ppi_8Security status. Security_status_ppi_9Security status. Security_status_ppi_10Security status. Security_status_ppi_11_GIC27Security status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Security_status_ppi_12_GIC28Security status. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Security_status_ppi_13_GIC29Security status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Security_status_ppi_14_GIC30Security status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Security_status_ppi_15_GIC31Security status. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDISR1 Security_status_spi_0_GIC32Security status. Security_status_spi_1_GIC33Security status. Security_status_spi_2_GIC34Security status. Security_status_spi_3_GIC35Security status. Security_status_spi_4_GIC36Security status. Security_status_spi_5_GIC37Security status. Security_status_spi_6_GIC38Security status. Security_status_spi_7_GIC39Security status. Security_status_spi_8_GIC40Security status. Security_status_spi_9_GIC41Security status. Security_status_spi_10_GIC42Security status. Security_status_spi_11_GIC43Security status. Security_status_spi_12_GIC44Security status. Security_status_spi_13_GIC45Security status. Security_status_spi_14_GIC46Security status. Security_status_spi_15_GIC47Security status. Security_status_spi_16_GIC48Security status. Security_status_spi_17_GIC49Security status. Security_status_spi_18_GIC50Security status. Security_status_spi_19_GIC51Security status. Security_status_spi_20_GIC52Security status. Security_status_spi_21_GIC53Security status. Security_status_spi_22_GIC54Security status. Security_status_spi_23_GIC55Security status. Security_status_spi_24_GIC56Security status. Security_status_spi_25_GIC57Security status. Security_status_spi_26_GIC58Security status. Security_status_spi_27_GIC59Security status. Security_status_spi_28_GIC60Security status. Security_status_spi_29_GIC61Security status. Security_status_spi_30_GIC62Security status. Security_status_spi_31_GIC63Security status. ICDISR2 Security_status_spi_32_GIC64Security status. Security_status_spi_33_GIC65Security status. Security_status_spi_34_GIC66Security status. Security_status_spi_35_GIC67Security status. Security_status_spi_36_GIC68Security status. Security_status_spi_37_GIC69Security status. Security_status_spi_38_GIC70Security status. Security_status_spi_39_GIC71Security status. Security_status_spi_40_GIC72Security status. Security_status_spi_41_GIC73Security status. Security_status_spi_42_GIC74Security status. Security_status_spi_43_GIC75Security status. Security_status_spi_44_GIC76Security status. Security_status_spi_45_GIC77Security status. Security_status_spi_46_GIC78Security status. Security_status_spi_47_GIC79Security status. Security_status_spi_48_GIC80Security status. Security_status_spi_49_GIC81Security status. Security_status_spi_50_GIC82Security status. Security_status_spi_51_GIC83Security status. Security_status_spi_52_GIC84Security status. Security_status_spi_53_GIC85Security status. Security_status_spi_54_GIC86Security status. Security_status_spi_55_GIC87Security status. Security_status_spi_56_GIC88Security status. Security_status_spi_57_GIC89Security status. Security_status_spi_58_GIC90Security status. Security_status_spi_59_GIC91Security status. Security_status_spi_60_GIC92Security status. Security_status_spi_61_GIC93Security status. Security_status_spi_62_GIC94Security status. Security_status_spi_63_GIC95Security status. ICDISR3 Security_status_spi_64_GIC96Security status. Security_status_spi_65_GIC97Security status. Security_status_spi_66_GIC98Security status. Security_status_spi_67_GIC99Security status. Security_status_spi_68_GIC100Security status. Security_status_spi_69_GIC101Security status. Security_status_spi_70_GIC102Security status. Security_status_spi_71_GIC103Security status. Security_status_spi_72_GIC104Security status. Security_status_spi_73_GIC105Security status. Security_status_spi_74_GIC106Security status. Security_status_spi_75_GIC107Security status. Security_status_spi_76_GIC108Security status. Security_status_spi_77_GIC109Security status. Security_status_spi_78_GIC110Security status. Security_status_spi_79_GIC111Security status. Security_status_spi_80_GIC112Security status. Security_status_spi_81_GIC113Security status. Security_status_spi_82_GIC114Security status. Security_status_spi_83_GIC115Security status. Security_status_spi_84_GIC116Security status. Security_status_spi_85_GIC117Security status. Security_status_spi_86_GIC118Security status. Security_status_spi_87_GIC119Security status. Security_status_spi_88_GIC120Security status. Security_status_spi_89_GIC121Security status. Security_status_spi_90_GIC122Security status. Security_status_spi_91_GIC123Security status. Security_status_spi_92_GIC124Security status. Security_status_spi_93_GIC125Security status. Security_status_spi_94_GIC126Security status. Security_status_spi_95_GIC127Security status. ICDISR4 Security_status_spi_96_GIC128Security status. Security_status_spi_97_GIC129Security status. Security_status_spi_98_GIC130Security status. Security_status_spi_99_GIC131Security status. Security_status_spi_100_GIC132Security status. Security_status_spi_101_GIC133Security status. Security_status_spi_102_GIC134Security status. Security_status_spi_103_GIC135Security status. Security_status_spi_104_GIC136Security status. Security_status_spi_105_GIC137Security status. Security_status_spi_106_GIC138Security status. Security_status_spi_107_GIC139Security status. Security_status_spi_108_GIC140Security status. Security_status_spi_109_GIC141Security status. Security_status_spi_110_GIC142Security status. Security_status_spi_111_GIC143Security status. Security_status_spi_112_GIC144Security status. Security_status_spi_113_GIC145Security status. Security_status_spi_114_GIC146Security status. Security_status_spi_115_GIC147Security status. Security_status_spi_116_GIC148Security status. Security_status_spi_117_GIC149Security status. Security_status_spi_118_GIC150Security status. Security_status_spi_119_GIC151Security status. Security_status_spi_120_GIC152Security status. Security_status_spi_121_GIC153Security status. Security_status_spi_122_GIC154Security status. Security_status_spi_123_GIC155Security status. Security_status_spi_124_GIC156Security status. Security_status_spi_125_GIC157Security status. Security_status_spi_126_GIC158Security status. Security_status_spi_127_GIC159Security status. ICDISR5 Security_status_spi_128_GIC160Security status. Security_status_spi_129_GIC161Security status. Security_status_spi_130_GIC162Security status. Security_status_spi_131_GIC163Security status. Security_status_spi_132_GIC164Security status. Security_status_spi_133_GIC165Security status. Security_status_spi_134_GIC166Security status. Security_status_spi_135_GIC167Security status. Security_status_spi_136_GIC168Security status. Security_status_spi_137_GIC169Security status. Security_status_spi_138_GIC170Security status. Security_status_spi_139_GIC171Security status. Security_status_spi_140_GIC172Security status. Security_status_spi_141_GIC173Security status. Security_status_spi_142_GIC174Security status. Security_status_spi_143_GIC175Security status. Security_status_spi_144_GIC176Security status. Security_status_spi_145_GIC177Security status. Security_status_spi_146_GIC178Security status. Security_status_spi_147_GIC179Security status. Security_status_spi_148_GIC180Security status. Security_status_spi_149_GIC181Security status. Security_status_spi_150_GIC182Security status. Security_status_spi_151_GIC183Security status. Security_status_spi_152_GIC184Security status. Security_status_spi_153_GIC185Security status. Security_status_spi_154_GIC186Security status. Security_status_spi_155_GIC187Security status. Security_status_spi_156_GIC188Security status. Security_status_spi_157_GIC189Security status. Security_status_spi_158_GIC190Security status. Security_status_spi_159_GIC191Security status. ICDISR6 Security_status_spi_160_GIC192Security status. Security_status_spi_161_GIC193Security status. Security_status_spi_162_GIC194Security status. Security_status_spi_163_GIC195Security status. Security_status_spi_164_GIC196Security status. Security_status_spi_165_GIC197Security status. Security_status_spi_166_GIC198Security status. Security_status_spi_167_GIC199Security status. Security_status_spi_168_GIC200Security status. Security_status_spi_169_GIC201Security status. Security_status_spi_170_GIC202Security status. Security_status_spi_171_GIC203Security status. Security_status_spi_172_GIC204Security status. Security_status_spi_173_GIC205Security status. Security_status_spi_174_GIC206Security status. Security_status_spi_175_GIC207Security status. Security_status_spi_176_GIC208Security status. Security_status_spi_177_GIC209Security status. Security_status_spi_178_GIC210Security status. Security_status_spi_179_GIC211Security status. ICDISER0 4.3.5 Interrupt Set-Enable Registers, GICD_ISENABLERn The GICD_ISENABLER characteristics are: Purpose The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. Writing 1 to a Set-enable bit enables forwarding of the corresponding interrupt from the Distributor to the CPU interfaces. Reading a bit identifies whether the interrupt is enabled. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions: * a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses * if the GIC implements configuration lockdown, the system can lock down the Set-enable bits for the lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82. Whether implemented SGIs are permanently enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and GICD_ICENABLER0, is IMPLEMENTATION DEFINED. Attributes RW ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.4 Interrupt Set-Enable Registers This section describes the implementation defined features of the ICDISERn. In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits in the ICDISERn are read as one, write ignored. Set_enable_sgi_0For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_1For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_2For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_3For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_4For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_5For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_6For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_7For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_8For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_9For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_10For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_11For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_12For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_13For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_14For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_sgi_15For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_0For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_1For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_2For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_3For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_4For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_5For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_6For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_7For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_8For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_9For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_10For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_ppi_11_GIC27For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Set_enable_ppi_12_GIC28For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Set_enable_ppi_13_GIC29For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Set_enable_ppi_14_GIC30For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Set_enable_ppi_15_GIC31For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDISER1 Set_enable_spi_0_GIC32For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_1_GIC33For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_2_GIC34For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_3_GIC35For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_4_GIC36For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_5_GIC37For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_6_GIC38For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_7_GIC39For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_8_GIC40For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_9_GIC41For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_10_GIC42For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_11_GIC43For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_12_GIC44For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_13_GIC45For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_14_GIC46For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_15_GIC47For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_16_GIC48For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_17_GIC49For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_18_GIC50For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_19_GIC51For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_20_GIC52For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_21_GIC53For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_22_GIC54For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_23_GIC55For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_24_GIC56For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_25_GIC57For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_26_GIC58For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_27_GIC59For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_28_GIC60For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_29_GIC61For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_30_GIC62For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_31_GIC63For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISER2 Set_enable_spi_32_GIC64For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_33_GIC65For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_34_GIC66For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_35_GIC67For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_36_GIC68For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_37_GIC69For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_38_GIC70For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_39_GIC71For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_40_GIC72For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_41_GIC73For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_42_GIC74For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_43_GIC75For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_44_GIC76For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_45_GIC77For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_46_GIC78For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_47_GIC79For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_48_GIC80For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_49_GIC81For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_50_GIC82For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_51_GIC83For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_52_GIC84For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_53_GIC85For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_54_GIC86For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_55_GIC87For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_56_GIC88For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_57_GIC89For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_58_GIC90For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_59_GIC91For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_60_GIC92For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_61_GIC93For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_62_GIC94For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_63_GIC95For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISER3 Set_enable_spi_64_GIC96For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_65_GIC97For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_66_GIC98For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_67_GIC99For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_68_GIC100For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_69_GIC101For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_70_GIC102For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_71_GIC103For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_72_GIC104For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_73_GIC105For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_74_GIC106For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_75_GIC107For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_76_GIC108For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_77_GIC109For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_78_GIC110For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_79_GIC111For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_80_GIC112For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_81_GIC113For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_82_GIC114For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_83_GIC115For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_84_GIC116For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_85_GIC117For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_86_GIC118For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_87_GIC119For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_88_GIC120For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_89_GIC121For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_90_GIC122For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_91_GIC123For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_92_GIC124For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_93_GIC125For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_94_GIC126For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_95_GIC127For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISER4 Set_enable_spi_96_GIC128For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_97_GIC129For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_98_GIC130For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_99_GIC131For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_100_GIC132For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_101_GIC133For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_102_GIC134For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_103_GIC135For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_104_GIC136For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_105_GIC137For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_106_GIC138For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_107_GIC139For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_108_GIC140For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_109_GIC141For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_110_GIC142For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_111_GIC143For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_112_GIC144For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_113_GIC145For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_114_GIC146For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_115_GIC147For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_116_GIC148For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_117_GIC149For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_118_GIC150For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_119_GIC151For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_120_GIC152For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_121_GIC153For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_122_GIC154For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_123_GIC155For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_124_GIC156For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_125_GIC157For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_126_GIC158For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_127_GIC159For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISER5 Set_enable_spi_128_GIC160For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_129_GIC161For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_130_GIC162For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_131_GIC163For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_132_GIC164For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_133_GIC165For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_134_GIC166For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_135_GIC167For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_136_GIC168For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_137_GIC169For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_138_GIC170For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_139_GIC171For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_140_GIC172For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_141_GIC173For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_142_GIC174For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_143_GIC175For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_144_GIC176For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_145_GIC177For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_146_GIC178For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_147_GIC179For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_148_GIC180For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_149_GIC181For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_150_GIC182For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_151_GIC183For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_152_GIC184For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_153_GIC185For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_154_GIC186For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_155_GIC187For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_156_GIC188For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_157_GIC189For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_158_GIC190For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_159_GIC191For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISER6 Set_enable_spi_160_GIC192For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_161_GIC193For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_162_GIC194For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_163_GIC195For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_164_GIC196For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_165_GIC197For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_166_GIC198For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_167_GIC199For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_168_GIC200For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_169_GIC201For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_170_GIC202For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_171_GIC203For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_172_GIC204For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_173_GIC205For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_174_GIC206For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_175_GIC207For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_176_GIC208For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_177_GIC209For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_178_GIC210For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Set_enable_spi_179_GIC211For SPIs and PPIs: writes 0 = Has no effect / 1 = Set-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER0 Interrupt Clear-Enable Registers (n) 4.3.6 Interrupt Clear-Enable Registers, GICD_ICENABLERn The GICD_ICENABLER characteristics are: Purpose The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. Writing 1 to a Clear-enable bit disables forwarding of the corresponding interrupt from the Distributor to the CPU interfaces. Reading a bit identifies whether the interrupt is enabled. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions: * a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses * if the GIC implements configuration lockdown, the system can lock down the Clear-enable bits for the lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82. Whether implemented SGIs are permanently enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and GICD_ICENABLER0, is IMPLEMENTATION DEFINED. Configurations These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common. The number of implemented GICD_ICENABLERs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ICENABLERs number upwards from GICD_ICENABLER0. In a multiprocessor implementation, GICD_ICENABLER0 is banked for each connected processor. This register holds the Clear-enable bits for interrupts 0-31. Attributes RW ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.5 Interrupt Clear-Enable Registers This section describes the implementation defined features of the ICDICERn. In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits in the ICDICERn are read as one, write ignored. Clear_enable_sgi_0For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_1For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_2For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_3For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_4For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_5For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_6For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_7For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_8For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_9For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_10For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_11For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_12For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_13For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_14For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_sgi_15For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_0For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_1For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_2For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_3For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_4For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_5For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_6For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_7For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_8For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_9For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_10For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_ppi_11_GIC27For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Clear_enable_ppi_12_GIC28For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Clear_enable_ppi_13_GIC29For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Clear_enable_ppi_14_GIC30For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Clear_enable_ppi_15_GIC31For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDICER1 Clear_enable_spi_0_GIC32For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_1_GIC33For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_2_GIC34For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_3_GIC35For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_4_GIC36For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_5_GIC37For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_6_GIC38For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_7_GIC39For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_8_GIC40For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_9_GIC41For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_10_GIC42For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_11_GIC43For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_12_GIC44For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_13_GIC45For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_14_GIC46For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_15_GIC47For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_16_GIC48For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_17_GIC49For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_18_GIC50For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_19_GIC51For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_20_GIC52For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_21_GIC53For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_22_GIC54For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_23_GIC55For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_24_GIC56For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_25_GIC57For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_26_GIC58For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_27_GIC59For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_28_GIC60For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_29_GIC61For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_30_GIC62For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_31_GIC63For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER2 Clear_enable_spi_32_GIC64For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_33_GIC65For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_34_GIC66For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_35_GIC67For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_36_GIC68For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_37_GIC69For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_38_GIC70For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_39_GIC71For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_40_GIC72For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_41_GIC73For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_42_GIC74For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_43_GIC75For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_44_GIC76For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_45_GIC77For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_46_GIC78For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_47_GIC79For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_48_GIC80For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_49_GIC81For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_50_GIC82For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_51_GIC83For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_52_GIC84For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_53_GIC85For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_54_GIC86For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_55_GIC87For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_56_GIC88For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_57_GIC89For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_58_GIC90For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_59_GIC91For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_60_GIC92For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_61_GIC93For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_62_GIC94For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_63_GIC95For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER3 Clear_enable_spi_64_GIC96For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_65_GIC97For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_66_GIC98For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_67_GIC99For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_68_GIC100For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_69_GIC101For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_70_GIC102For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_71_GIC103For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_72_GIC104For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_73_GIC105For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_74_GIC106For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_75_GIC107For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_76_GIC108For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_77_GIC109For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_78_GIC110For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_79_GIC111For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_80_GIC112For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_81_GIC113For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_82_GIC114For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_83_GIC115For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_84_GIC116For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_85_GIC117For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_86_GIC118For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_87_GIC119For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_88_GIC120For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_89_GIC121For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_90_GIC122For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_91_GIC123For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_92_GIC124For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_93_GIC125For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_94_GIC126For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_95_GIC127For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER4 Clear_enable_spi_96_GIC128For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_97_GIC129For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_98_GIC130For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_99_GIC131For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_100_GIC132For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_101_GIC133For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_102_GIC134For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_103_GIC135For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_104_GIC136For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_105_GIC137For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_106_GIC138For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_107_GIC139For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_108_GIC140For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_109_GIC141For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_110_GIC142For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_111_GIC143For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_112_GIC144For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_113_GIC145For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_114_GIC146For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_115_GIC147For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_116_GIC148For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_117_GIC149For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_118_GIC150For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_119_GIC151For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_120_GIC152For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_121_GIC153For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_122_GIC154For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_123_GIC155For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_124_GIC156For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_125_GIC157For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_126_GIC158For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_127_GIC159For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER5 Clear_enable_spi_128_GIC160For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_129_GIC161For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_130_GIC162For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_131_GIC163For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_132_GIC164For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_133_GIC165For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_134_GIC166For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_135_GIC167For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_136_GIC168For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_137_GIC169For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_138_GIC170For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_139_GIC171For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_140_GIC172For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_141_GIC173For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_142_GIC174For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_143_GIC175For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_144_GIC176For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_145_GIC177For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_146_GIC178For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_147_GIC179For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_148_GIC180For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_149_GIC181For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_150_GIC182For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_151_GIC183For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_152_GIC184For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_153_GIC185For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_154_GIC186For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_155_GIC187For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_156_GIC188For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_157_GIC189For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_158_GIC190For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_159_GIC191For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDICER6 Clear_enable_spi_160_GIC192For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_161_GIC193For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_162_GIC194For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_163_GIC195For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_164_GIC196For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_165_GIC197For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_166_GIC198For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_167_GIC199For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_168_GIC200For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_169_GIC201For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_170_GIC202For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_171_GIC203For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_172_GIC204For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_173_GIC205For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_174_GIC206For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_175_GIC207For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_176_GIC208For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_177_GIC209For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_178_GIC210For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. Clear_enable_spi_179_GIC211For SPIs and PPIs: writes 0 = Has no effect / 1 = Clear-Enable. For SGIs the behavior of the bit on reads and writes is IMPLEMENTATION DEFINED. ICDISPR0 Interrupt Set-Pending Registers (n) 4.3.7 Interrupt Set-Pending Registers, GICD_ISPENDRn The GICD_ISPENDR characteristics are: Purpose The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC. Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending. Reading a bit identifies whether the interrupt is pending. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions: * a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses * if the GIC implements configuration lockdown, the system can lock down the Set-pending bits for the lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82. Set-pending bits for SGIs are read-only and ignore writes. Configurations These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common. The number of implemented GICD_ISPENDRs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ISPENDRs number upwards from GICD_ISPENDR0. In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31. Attributes RW Set_pending_sgi_0For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_1For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_2For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_3For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_4For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_5For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_6For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_7For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_8For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_9For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_10For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_11For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_12For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_13For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_14For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_sgi_15For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_0For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_1For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_2For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_3For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_4For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_5For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_6For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_7For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_8For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_9For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_10For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_ppi_11_GIC27For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Set_pending_ppi_12_GIC28For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Set_pending_ppi_13_GIC29For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Set_pending_ppi_14_GIC30For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Set_pending_ppi_15_GIC31For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDISPR1 Set_pending_spi_0_GIC32For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_1_GIC33For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_2_GIC34For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_3_GIC35For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_4_GIC36For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_5_GIC37For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_6_GIC38For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_7_GIC39For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_8_GIC40For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_9_GIC41For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_10_GIC42For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_11_GIC43For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_12_GIC44For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_13_GIC45For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_14_GIC46For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_15_GIC47For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_16_GIC48For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_17_GIC49For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_18_GIC50For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_19_GIC51For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_20_GIC52For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_21_GIC53For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_22_GIC54For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_23_GIC55For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_24_GIC56For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_25_GIC57For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_26_GIC58For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_27_GIC59For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_28_GIC60For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_29_GIC61For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_30_GIC62For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_31_GIC63For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDISPR2 Set_pending_spi_32_GIC64For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_33_GIC65For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_34_GIC66For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_35_GIC67For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_36_GIC68For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_37_GIC69For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_38_GIC70For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_39_GIC71For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_40_GIC72For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_41_GIC73For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_42_GIC74For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_43_GIC75For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_44_GIC76For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_45_GIC77For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_46_GIC78For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_47_GIC79For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_48_GIC80For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_49_GIC81For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_50_GIC82For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_51_GIC83For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_52_GIC84For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_53_GIC85For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_54_GIC86For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_55_GIC87For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_56_GIC88For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_57_GIC89For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_58_GIC90For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_59_GIC91For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_60_GIC92For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_61_GIC93For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_62_GIC94For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_63_GIC95For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDISPR3 Set_pending_spi_64_GIC96For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_65_GIC97For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_66_GIC98For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_67_GIC99For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_68_GIC100For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_69_GIC101For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_70_GIC102For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_71_GIC103For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_72_GIC104For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_73_GIC105For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_74_GIC106For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_75_GIC107For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_76_GIC108For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_77_GIC109For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_78_GIC110For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_79_GIC111For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_80_GIC112For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_81_GIC113For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_82_GIC114For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_83_GIC115For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_84_GIC116For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_85_GIC117For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_86_GIC118For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_87_GIC119For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_88_GIC120For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_89_GIC121For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_90_GIC122For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_91_GIC123For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_92_GIC124For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_93_GIC125For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_94_GIC126For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_95_GIC127For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDISPR4 Set_pending_spi_96_GIC128For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_97_GIC129For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_98_GIC130For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_99_GIC131For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_100_GIC132For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_101_GIC133For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_102_GIC134For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_103_GIC135For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_104_GIC136For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_105_GIC137For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_106_GIC138For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_107_GIC139For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_108_GIC140For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_109_GIC141For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_110_GIC142For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_111_GIC143For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_112_GIC144For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_113_GIC145For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_114_GIC146For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_115_GIC147For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_116_GIC148For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_117_GIC149For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_118_GIC150For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_119_GIC151For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_120_GIC152For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_121_GIC153For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_122_GIC154For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_123_GIC155For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_124_GIC156For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_125_GIC157For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_126_GIC158For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_127_GIC159For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDISPR5 Set_pending_spi_128_GIC160For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_129_GIC161For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_130_GIC162For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_131_GIC163For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_132_GIC164For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_133_GIC165For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_134_GIC166For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_135_GIC167For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_136_GIC168For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_137_GIC169For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_138_GIC170For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_139_GIC171For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_140_GIC172For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_141_GIC173For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_142_GIC174For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_143_GIC175For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_144_GIC176For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_145_GIC177For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_146_GIC178For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_147_GIC179For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_148_GIC180For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_149_GIC181For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_150_GIC182For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_151_GIC183For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_152_GIC184For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_153_GIC185For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_154_GIC186For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_155_GIC187For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_156_GIC188For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_157_GIC189For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_158_GIC190For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_159_GIC191For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDISPR6 Set_pending_spi_160_GIC192For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_161_GIC193For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_162_GIC194For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_163_GIC195For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_164_GIC196For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_165_GIC197For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_166_GIC198For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_167_GIC199For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_168_GIC200For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_169_GIC201For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_170_GIC202For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_171_GIC203For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_172_GIC204For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_173_GIC205For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_174_GIC206For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_175_GIC207For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_176_GIC208For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_177_GIC209For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_178_GIC210For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. Set_pending_spi_179_GIC211For SPIs and PPIs: write 0 = Has no effect / 1 = Set-Pending. For SGIs, the write is ignored. ICDICPR0 Interrupt Clear-Pending Registers (n) 4.3.8 Interrupt Clear-Pending Registers, GICD_ICPENDRn The GICD_ICPENDR characteristics are: Purpose The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. Writing 1 to a Clear-pending bit clears the pending state of the corresponding peripheral interrupt. Reading a bit identifies whether the interrupt is pending. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions: * a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses * if the GIC implements configuration lockdown, the system can lock down the Clear-pending bits for the lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82. Clear-pending bits for SGIs are read-only and ignore writes. Configurations These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common. The number of implemented GICD_ICPENDRs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ICPENDRs number upwards from GICD_ICPENDR0. In a multiprocessor implementation, GICD_ICPENDR0 is banked for each connected processor. This register holds the Clear-pending bits for interrupts 0-31. Attributes RW Clear_pending_sgi_0For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_1For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_2For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_3For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_4For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_5For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_6For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_7For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_8For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_9For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_10For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_11For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_12For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_13For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_14For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_sgi_15For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_0For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_1For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_2For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_3For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_4For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_5For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_6For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_7For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_8For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_9For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_10For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_ppi_11_GIC27For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Clear_pending_ppi_12_GIC28For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Clear_pending_ppi_13_GIC29For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Clear_pending_ppi_14_GIC30For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Clear_pending_ppi_15_GIC31For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDICPR1 Clear_pending_spi_0_GIC32For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_1_GIC33For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_2_GIC34For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_3_GIC35For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_4_GIC36For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_5_GIC37For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_6_GIC38For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_7_GIC39For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_8_GIC40For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_9_GIC41For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_10_GIC42For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_11_GIC43For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_12_GIC44For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_13_GIC45For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_14_GIC46For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_15_GIC47For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_16_GIC48For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_17_GIC49For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_18_GIC50For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_19_GIC51For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_20_GIC52For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_21_GIC53For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_22_GIC54For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_23_GIC55For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_24_GIC56For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_25_GIC57For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_26_GIC58For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_27_GIC59For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_28_GIC60For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_29_GIC61For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_30_GIC62For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_31_GIC63For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDICPR2 Clear_pending_spi_32_GIC64For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_33_GIC65For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_34_GIC66For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_35_GIC67For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_36_GIC68For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_37_GIC69For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_38_GIC70For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_39_GIC71For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_40_GIC72For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_41_GIC73For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_42_GIC74For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_43_GIC75For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_44_GIC76For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_45_GIC77For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_46_GIC78For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_47_GIC79For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_48_GIC80For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_49_GIC81For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_50_GIC82For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_51_GIC83For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_52_GIC84For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_53_GIC85For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_54_GIC86For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_55_GIC87For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_56_GIC88For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_57_GIC89For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_58_GIC90For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_59_GIC91For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_60_GIC92For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_61_GIC93For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_62_GIC94For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_63_GIC95For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDICPR3 Clear_pending_spi_64_GIC96For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_65_GIC97For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_66_GIC98For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_67_GIC99For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_68_GIC100For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_69_GIC101For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_70_GIC102For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_71_GIC103For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_72_GIC104For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_73_GIC105For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_74_GIC106For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_75_GIC107For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_76_GIC108For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_77_GIC109For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_78_GIC110For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_79_GIC111For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_80_GIC112For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_81_GIC113For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_82_GIC114For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_83_GIC115For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_84_GIC116For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_85_GIC117For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_86_GIC118For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_87_GIC119For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_88_GIC120For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_89_GIC121For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_90_GIC122For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_91_GIC123For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_92_GIC124For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_93_GIC125For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_94_GIC126For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_95_GIC127For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDICPR4 Clear_pending_spi_96_GIC128For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_97_GIC129For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_98_GIC130For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_99_GIC131For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_100_GIC132For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_101_GIC133For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_102_GIC134For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_103_GIC135For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_104_GIC136For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_105_GIC137For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_106_GIC138For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_107_GIC139For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_108_GIC140For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_109_GIC141For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_110_GIC142For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_111_GIC143For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_112_GIC144For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_113_GIC145For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_114_GIC146For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_115_GIC147For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_116_GIC148For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_117_GIC149For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_118_GIC150For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_119_GIC151For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_120_GIC152For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_121_GIC153For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_122_GIC154For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_123_GIC155For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_124_GIC156For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_125_GIC157For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_126_GIC158For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_127_GIC159For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDICPR5 Clear_pending_spi_128_GIC160For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_129_GIC161For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_130_GIC162For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_131_GIC163For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_132_GIC164For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_133_GIC165For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_134_GIC166For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_135_GIC167For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_136_GIC168For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_137_GIC169For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_138_GIC170For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_139_GIC171For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_140_GIC172For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_141_GIC173For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_142_GIC174For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_143_GIC175For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_144_GIC176For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_145_GIC177For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_146_GIC178For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_147_GIC179For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_148_GIC180For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_149_GIC181For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_150_GIC182For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_151_GIC183For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_152_GIC184For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_153_GIC185For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_154_GIC186For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_155_GIC187For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_156_GIC188For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_157_GIC189For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_158_GIC190For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_159_GIC191For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDICPR6 Clear_pending_spi_160_GIC192For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_161_GIC193For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_162_GIC194For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_163_GIC195For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_164_GIC196For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_165_GIC197For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_166_GIC198For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_167_GIC199For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_168_GIC200For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_169_GIC201For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_170_GIC202For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_171_GIC203For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_172_GIC204For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_173_GIC205For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_174_GIC206For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_175_GIC207For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_176_GIC208For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_177_GIC209For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_178_GIC210For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. Clear_pending_spi_179_GIC211For SPIs and PPIs: write 0 = Has no effect / 1 = Clear-Pending. For SGIs, the write is ignored. ICDABR0 Active Bit registers (n) 4.3.10 Interrupt Clear-Active Registers, GICD_ICACTIVERn / Active Bit Registers, ICDABRn ## In GICv1, these are the Active Bit Registers, ICDABRn. These registers are RO. The GICD_ICACTIVER characteristics are: Purpose The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC supports. Writing to a Clear-active bit Deactivates the corresponding interrupt. These registers are used when preserving and restoring GIC state. Usage constraints A register bit corresponding to an unimplemented interrupt is RAZ/WI. If the GIC implements the Security Extensions, a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses. Configurations These registers are present only in GICv2. The register locations are reserved in GICv1. The number of implemented GICD_ICACTIVERs is (GICD_TYPER.ITLinesNumber+1). The implemented GICD_ICACTIVERs number upwards from GICD_ICACTIVER0. In a multiprocessor implementation, GICD_ICACTIVER0 is banked for each connected processor. This register holds the Clear-active bits for interrupts 0-31. Attributes RO Active_status_sgi_0Active status. Active_status_sgi_1Active status. Active_status_sgi_2Active status. Active_status_sgi_3Active status. Active_status_sgi_4Active status. Active_status_sgi_5Active status. Active_status_sgi_6Active status. Active_status_sgi_7Active status. Active_status_sgi_8Active status. Active_status_sgi_9Active status. Active_status_sgi_10Active status. Active_status_sgi_11Active status. Active_status_sgi_12Active status. Active_status_sgi_13Active status. Active_status_sgi_14Active status. Active_status_sgi_15Active status. Active_status_ppi_0Active status. Active_status_ppi_1Active status. Active_status_ppi_2Active status. Active_status_ppi_3Active status. Active_status_ppi_4Active status. Active_status_ppi_5Active status. Active_status_ppi_6Active status. Active_status_ppi_7Active status. Active_status_ppi_8Active status. Active_status_ppi_9Active status. Active_status_ppi_10Active status. Active_status_ppi_11_GIC27Active status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. Active_status_ppi_12_GIC28Active status. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Active_status_ppi_13_GIC29Active status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Active_status_ppi_14_GIC30Active status. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Active_status_ppi_15_GIC31Active status. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDABR1 Active_status_spi_0_GIC32Active status. Active_status_spi_1_GIC33Active status. Active_status_spi_2_GIC34Active status. Active_status_spi_3_GIC35Active status. Active_status_spi_4_GIC36Active status. Active_status_spi_5_GIC37Active status. Active_status_spi_6_GIC38Active status. Active_status_spi_7_GIC39Active status. Active_status_spi_8_GIC40Active status. Active_status_spi_9_GIC41Active status. Active_status_spi_10_GIC42Active status. Active_status_spi_11_GIC43Active status. Active_status_spi_12_GIC44Active status. Active_status_spi_13_GIC45Active status. Active_status_spi_14_GIC46Active status. Active_status_spi_15_GIC47Active status. Active_status_spi_16_GIC48Active status. Active_status_spi_17_GIC49Active status. Active_status_spi_18_GIC50Active status. Active_status_spi_19_GIC51Active status. Active_status_spi_20_GIC52Active status. Active_status_spi_21_GIC53Active status. Active_status_spi_22_GIC54Active status. Active_status_spi_23_GIC55Active status. Active_status_spi_24_GIC56Active status. Active_status_spi_25_GIC57Active status. Active_status_spi_26_GIC58Active status. Active_status_spi_27_GIC59Active status. Active_status_spi_28_GIC60Active status. Active_status_spi_29_GIC61Active status. Active_status_spi_30_GIC62Active status. Active_status_spi_31_GIC63Active status. ICDABR2 Active_status_spi_32_GIC64Active status. Active_status_spi_33_GIC65Active status. Active_status_spi_34_GIC66Active status. Active_status_spi_35_GIC67Active status. Active_status_spi_36_GIC68Active status. Active_status_spi_37_GIC69Active status. Active_status_spi_38_GIC70Active status. Active_status_spi_39_GIC71Active status. Active_status_spi_40_GIC72Active status. Active_status_spi_41_GIC73Active status. Active_status_spi_42_GIC74Active status. Active_status_spi_43_GIC75Active status. Active_status_spi_44_GIC76Active status. Active_status_spi_45_GIC77Active status. Active_status_spi_46_GIC78Active status. Active_status_spi_47_GIC79Active status. Active_status_spi_48_GIC80Active status. Active_status_spi_49_GIC81Active status. Active_status_spi_50_GIC82Active status. Active_status_spi_51_GIC83Active status. Active_status_spi_52_GIC84Active status. Active_status_spi_53_GIC85Active status. Active_status_spi_54_GIC86Active status. Active_status_spi_55_GIC87Active status. Active_status_spi_56_GIC88Active status. Active_status_spi_57_GIC89Active status. Active_status_spi_58_GIC90Active status. Active_status_spi_59_GIC91Active status. Active_status_spi_60_GIC92Active status. Active_status_spi_61_GIC93Active status. Active_status_spi_62_GIC94Active status. Active_status_spi_63_GIC95Active status. ICDABR3 Active_status_spi_64_GIC96Active status. Active_status_spi_65_GIC97Active status. Active_status_spi_66_GIC98Active status. Active_status_spi_67_GIC99Active status. Active_status_spi_68_GIC100Active status. Active_status_spi_69_GIC101Active status. Active_status_spi_70_GIC102Active status. Active_status_spi_71_GIC103Active status. Active_status_spi_72_GIC104Active status. Active_status_spi_73_GIC105Active status. Active_status_spi_74_GIC106Active status. Active_status_spi_75_GIC107Active status. Active_status_spi_76_GIC108Active status. Active_status_spi_77_GIC109Active status. Active_status_spi_78_GIC110Active status. Active_status_spi_79_GIC111Active status. Active_status_spi_80_GIC112Active status. Active_status_spi_81_GIC113Active status. Active_status_spi_82_GIC114Active status. Active_status_spi_83_GIC115Active status. Active_status_spi_84_GIC116Active status. Active_status_spi_85_GIC117Active status. Active_status_spi_86_GIC118Active status. Active_status_spi_87_GIC119Active status. Active_status_spi_88_GIC120Active status. Active_status_spi_89_GIC121Active status. Active_status_spi_90_GIC122Active status. Active_status_spi_91_GIC123Active status. Active_status_spi_92_GIC124Active status. Active_status_spi_93_GIC125Active status. Active_status_spi_94_GIC126Active status. Active_status_spi_95_GIC127Active status. ICDABR4 Active_status_spi_96_GIC128Active status. Active_status_spi_97_GIC129Active status. Active_status_spi_98_GIC130Active status. Active_status_spi_99_GIC131Active status. Active_status_spi_100_GIC132Active status. Active_status_spi_101_GIC133Active status. Active_status_spi_102_GIC134Active status. Active_status_spi_103_GIC135Active status. Active_status_spi_104_GIC136Active status. Active_status_spi_105_GIC137Active status. Active_status_spi_106_GIC138Active status. Active_status_spi_107_GIC139Active status. Active_status_spi_108_GIC140Active status. Active_status_spi_109_GIC141Active status. Active_status_spi_110_GIC142Active status. Active_status_spi_111_GIC143Active status. Active_status_spi_112_GIC144Active status. Active_status_spi_113_GIC145Active status. Active_status_spi_114_GIC146Active status. Active_status_spi_115_GIC147Active status. Active_status_spi_116_GIC148Active status. Active_status_spi_117_GIC149Active status. Active_status_spi_118_GIC150Active status. Active_status_spi_119_GIC151Active status. Active_status_spi_120_GIC152Active status. Active_status_spi_121_GIC153Active status. Active_status_spi_122_GIC154Active status. Active_status_spi_123_GIC155Active status. Active_status_spi_124_GIC156Active status. Active_status_spi_125_GIC157Active status. Active_status_spi_126_GIC158Active status. Active_status_spi_127_GIC159Active status. ICDABR5 Active_status_spi_128_GIC160Active status. Active_status_spi_129_GIC161Active status. Active_status_spi_130_GIC162Active status. Active_status_spi_131_GIC163Active status. Active_status_spi_132_GIC164Active status. Active_status_spi_133_GIC165Active status. Active_status_spi_134_GIC166Active status. Active_status_spi_135_GIC167Active status. Active_status_spi_136_GIC168Active status. Active_status_spi_137_GIC169Active status. Active_status_spi_138_GIC170Active status. Active_status_spi_139_GIC171Active status. Active_status_spi_140_GIC172Active status. Active_status_spi_141_GIC173Active status. Active_status_spi_142_GIC174Active status. Active_status_spi_143_GIC175Active status. Active_status_spi_144_GIC176Active status. Active_status_spi_145_GIC177Active status. Active_status_spi_146_GIC178Active status. Active_status_spi_147_GIC179Active status. Active_status_spi_148_GIC180Active status. Active_status_spi_149_GIC181Active status. Active_status_spi_150_GIC182Active status. Active_status_spi_151_GIC183Active status. Active_status_spi_152_GIC184Active status. Active_status_spi_153_GIC185Active status. Active_status_spi_154_GIC186Active status. Active_status_spi_155_GIC187Active status. Active_status_spi_156_GIC188Active status. Active_status_spi_157_GIC189Active status. Active_status_spi_158_GIC190Active status. Active_status_spi_159_GIC191Active status. ICDABR6 Active_status_spi_160_GIC192Active status. Active_status_spi_161_GIC193Active status. Active_status_spi_162_GIC194Active status. Active_status_spi_163_GIC195Active status. Active_status_spi_164_GIC196Active status. Active_status_spi_165_GIC197Active status. Active_status_spi_166_GIC198Active status. Active_status_spi_167_GIC199Active status. Active_status_spi_168_GIC200Active status. Active_status_spi_169_GIC201Active status. Active_status_spi_170_GIC202Active status. Active_status_spi_171_GIC203Active status. Active_status_spi_172_GIC204Active status. Active_status_spi_173_GIC205Active status. Active_status_spi_174_GIC206Active status. Active_status_spi_175_GIC207Active status. Active_status_spi_176_GIC208Active status. Active_status_spi_177_GIC209Active status. Active_status_spi_178_GIC210Active status. Active_status_spi_179_GIC211Active status. ICDIPR0 4.3.11 Interrupt Priority Registers, GICD_IPRIORITYRn The GICD_IPRIORITYR characteristics are: Purpose The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the GIC. This field stores the priority of the corresponding interrupt. Usage constraints These registers are byte-accessible. A register field corresponding to an unimplemented interrupt is RAZ/WI. A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI. If the GIC implements the Security Extensions: * a register field that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses * a Non-secure access to a field that corresponds to a Group 1 interrupt behaves as described in Software views of interrupt priority in a GIC that includes the Security Extensions on page 3-53 * if the GIC implements configuration lockdown, the system can lock down the Priority fields for the lockable SPIs that are configured as Group 0, see Configuration lockdown on page 4-82 It is IMPLEMENTATION DEFINED whether changing the value of a priority field changes the priority of an active interrupt. Attributes RW Priority_sgi_0Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_1Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_2Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_3Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR1 Priority_sgi_4Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_5Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_6Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_7Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR2 Priority_sgi_8Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_9Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_10Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_11Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR3 Priority_sgi_12Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_13Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_14Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_sgi_15Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR4 Priority_ppi_0Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_1Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_2Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_3Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR5 Priority_ppi_4Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_5Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_6Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_7Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR6 Priority_ppi_8Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_9Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_10Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_ppi_11_GIC27Priority value. 0x00-0xF8 (0-248), in steps of 8. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. ICDIPR7 Priority_ppi_12_GIC28Priority value. 0x00-0xF8 (0-248), in steps of 8. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. Priority_ppi_13_GIC29Priority value. 0x00-0xF8 (0-248), in steps of 8. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. Priority_ppi_14_GIC30Priority value. 0x00-0xF8 (0-248), in steps of 8. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. Priority_ppi_15_GIC31Priority value. 0x00-0xF8 (0-248), in steps of 8. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDIPR8 Priority_spi_0_GIC32Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_1_GIC33Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_2_GIC34Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_3_GIC35Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR9 Priority_spi_4_GIC36Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_5_GIC37Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_6_GIC38Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_7_GIC39Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR10 Priority_spi_8_GIC40Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_9_GIC41Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_10_GIC42Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_11_GIC43Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR11 Priority_spi_12_GIC44Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_13_GIC45Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_14_GIC46Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_15_GIC47Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR12 Priority_spi_16_GIC48Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_17_GIC49Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_18_GIC50Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_19_GIC51Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR13 Priority_spi_20_GIC52Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_21_GIC53Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_22_GIC54Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_23_GIC55Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR14 Priority_spi_24_GIC56Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_25_GIC57Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_26_GIC58Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_27_GIC59Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR15 Priority_spi_28_GIC60Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_29_GIC61Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_30_GIC62Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_31_GIC63Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR16 Priority_spi_32_GIC64Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_33_GIC65Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_34_GIC66Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_35_GIC67Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR17 Priority_spi_36_GIC68Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_37_GIC69Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_38_GIC70Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_39_GIC71Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR18 Priority_spi_40_GIC72Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_41_GIC73Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_42_GIC74Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_43_GIC75Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR19 Priority_spi_44_GIC76Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_45_GIC77Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_46_GIC78Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_47_GIC79Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR20 Priority_spi_48_GIC80Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_49_GIC81Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_50_GIC82Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_51_GIC83Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR21 Priority_spi_52_GIC84Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_53_GIC85Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_54_GIC86Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_55_GIC87Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR22 Priority_spi_56_GIC88Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_57_GIC89Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_58_GIC90Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_59_GIC91Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR23 Priority_spi_60_GIC92Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_61_GIC93Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_62_GIC94Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_63_GIC95Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR24 Priority_spi_64_GIC96Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_65_GIC97Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_66_GIC98Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_67_GIC99Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR25 Priority_spi_68_GIC100Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_69_GIC101Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_70_GIC102Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_71_GIC103Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR26 Priority_spi_72_GIC104Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_73_GIC105Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_74_GIC106Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_75_GIC107Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR27 Priority_spi_76_GIC108Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_77_GIC109Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_78_GIC110Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_79_GIC111Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR28 Priority_spi_80_GIC112Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_81_GIC113Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_82_GIC114Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_83_GIC115Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR29 Priority_spi_84_GIC116Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_85_GIC117Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_86_GIC118Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_87_GIC119Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR30 Priority_spi_88_GIC120Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_89_GIC121Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_90_GIC122Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_91_GIC123Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR31 Priority_spi_92_GIC124Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_93_GIC125Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_94_GIC126Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_95_GIC127Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR32 Priority_spi_96_GIC128Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_97_GIC129Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_98_GIC130Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_99_GIC131Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR33 Priority_spi_100_GIC132Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_101_GIC133Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_102_GIC134Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_103_GIC135Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR34 Priority_spi_104_GIC136Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_105_GIC137Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_106_GIC138Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_107_GIC139Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR35 Priority_spi_108_GIC140Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_109_GIC141Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_110_GIC142Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_111_GIC143Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR36 Priority_spi_112_GIC144Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_113_GIC145Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_114_GIC146Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_115_GIC147Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR37 Priority_spi_116_GIC148Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_117_GIC149Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_118_GIC150Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_119_GIC151Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR38 Priority_spi_120_GIC152Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_121_GIC153Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_122_GIC154Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_123_GIC155Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR39 Priority_spi_124_GIC156Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_125_GIC157Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_126_GIC158Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_127_GIC159Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR40 Priority_spi_128_GIC160Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_129_GIC161Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_130_GIC162Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_131_GIC163Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR41 Priority_spi_132_GIC164Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_133_GIC165Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_134_GIC166Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_135_GIC167Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR42 Priority_spi_136_GIC168Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_137_GIC169Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_138_GIC170Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_139_GIC171Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR43 Priority_spi_140_GIC172Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_141_GIC173Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_142_GIC174Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_143_GIC175Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR44 Priority_spi_144_GIC176Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_145_GIC177Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_146_GIC178Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_147_GIC179Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR45 Priority_spi_148_GIC180Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_149_GIC181Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_150_GIC182Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_151_GIC183Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR46 Priority_spi_152_GIC184Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_153_GIC185Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_154_GIC186Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_155_GIC187Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR47 Priority_spi_156_GIC188Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_157_GIC189Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_158_GIC190Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_159_GIC191Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR48 Priority_spi_160_GIC192Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_161_GIC193Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_162_GIC194Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_163_GIC195Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR49 Priority_spi_164_GIC196Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_165_GIC197Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_166_GIC198Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_167_GIC199Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR50 Priority_spi_168_GIC200Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_169_GIC201Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_170_GIC202Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_171_GIC203Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR51 Priority_spi_172_GIC204Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_173_GIC205Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_174_GIC206Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_175_GIC207Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPR52 Priority_spi_176_GIC208Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_177_GIC209Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_178_GIC210Priority value. 0x00-0xF8 (0-248), in steps of 8. Priority_spi_179_GIC211Priority value. 0x00-0xF8 (0-248), in steps of 8. ICDIPTR0 4.3.12 Interrupt Processor Targets Registers, GICD_ITARGETSRn Purpose The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. Attributes RW ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.6 Interrupt Processor Targets Registers This section describes the implementation defined features of the ICDIPTRn. For systems that support only one Cortex-A9 processor, all these registers read as zero, and writes are ignored. The single Cortex-A9 processor is always set as the target of any interruption. For systems that support two or more Cortex-A9 processors, if the Processor Target field is set to 0 for a specific SPI, then this interrupt cannot be set pending through the hardware pins, nor by a write to the Set-Pending register. CPU_targets_sgi_0Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_1Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_2Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_3Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR1 CPU_targets_sgi_4Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_5Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_6Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_7Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR2 CPU_targets_sgi_8Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_9Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_10Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_11Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR3 CPU_targets_sgi_12Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_13Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_14Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_sgi_15Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR4 CPU_targets_ppi_0Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_1Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_2Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_3Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR5 CPU_targets_ppi_4Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_5Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_6Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_7Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR6 CPU_targets_ppi_8Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_9Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_10Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_ppi_11_GIC27Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. ICDIPTR7 CPU_targets_ppi_12_GIC28Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. CPU_targets_ppi_13_GIC29Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. CPU_targets_ppi_14_GIC30Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. CPU_targets_ppi_15_GIC31Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDIPTR8 CPU_targets_spi_0_GIC32Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_1_GIC33Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_2_GIC34Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_3_GIC35Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR9 CPU_targets_spi_4_GIC36Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_5_GIC37Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_6_GIC38Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_7_GIC39Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR10 CPU_targets_spi_8_GIC40Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_9_GIC41Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_10_GIC42Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_11_GIC43Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR11 CPU_targets_spi_12_GIC44Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_13_GIC45Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_14_GIC46Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_15_GIC47Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR12 CPU_targets_spi_16_GIC48Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_17_GIC49Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_18_GIC50Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_19_GIC51Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR13 CPU_targets_spi_20_GIC52Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_21_GIC53Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_22_GIC54Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_23_GIC55Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR14 CPU_targets_spi_24_GIC56Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_25_GIC57Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_26_GIC58Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_27_GIC59Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR15 CPU_targets_spi_28_GIC60Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_29_GIC61Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_30_GIC62Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_31_GIC63Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR16 CPU_targets_spi_32_GIC64Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_33_GIC65Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_34_GIC66Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_35_GIC67Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR17 CPU_targets_spi_36_GIC68Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_37_GIC69Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_38_GIC70Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_39_GIC71Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR18 CPU_targets_spi_40_GIC72Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_41_GIC73Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_42_GIC74Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_43_GIC75Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR19 CPU_targets_spi_44_GIC76Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_45_GIC77Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_46_GIC78Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_47_GIC79Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR20 CPU_targets_spi_48_GIC80Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_49_GIC81Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_50_GIC82Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_51_GIC83Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR21 CPU_targets_spi_52_GIC84Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_53_GIC85Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_54_GIC86Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_55_GIC87Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR22 CPU_targets_spi_56_GIC88Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_57_GIC89Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_58_GIC90Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_59_GIC91Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR23 CPU_targets_spi_60_GIC92Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_61_GIC93Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_62_GIC94Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_63_GIC95Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR24 CPU_targets_spi_64_GIC96Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_65_GIC97Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_66_GIC98Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_67_GIC99Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR25 CPU_targets_spi_68_GIC100Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_69_GIC101Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_70_GIC102Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_71_GIC103Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR26 CPU_targets_spi_72_GIC104Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_73_GIC105Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_74_GIC106Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_75_GIC107Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR27 CPU_targets_spi_76_GIC108Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_77_GIC109Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_78_GIC110Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_79_GIC111Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR28 CPU_targets_spi_80_GIC112Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_81_GIC113Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_82_GIC114Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_83_GIC115Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR29 CPU_targets_spi_84_GIC116Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_85_GIC117Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_86_GIC118Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_87_GIC119Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR30 CPU_targets_spi_88_GIC120Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_89_GIC121Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_90_GIC122Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_91_GIC123Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR31 CPU_targets_spi_92_GIC124Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_93_GIC125Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_94_GIC126Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_95_GIC127Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR32 CPU_targets_spi_96_GIC128Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_97_GIC129Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_98_GIC130Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_99_GIC131Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR33 CPU_targets_spi_100_GIC132Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_101_GIC133Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_102_GIC134Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_103_GIC135Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR34 CPU_targets_spi_104_GIC136Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_105_GIC137Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_106_GIC138Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_107_GIC139Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR35 CPU_targets_spi_108_GIC140Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_109_GIC141Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_110_GIC142Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_111_GIC143Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR36 CPU_targets_spi_112_GIC144Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_113_GIC145Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_114_GIC146Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_115_GIC147Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR37 CPU_targets_spi_116_GIC148Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_117_GIC149Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_118_GIC150Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_119_GIC151Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR38 CPU_targets_spi_120_GIC152Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_121_GIC153Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_122_GIC154Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_123_GIC155Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR39 CPU_targets_spi_124_GIC156Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_125_GIC157Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_126_GIC158Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_127_GIC159Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR40 CPU_targets_spi_128_GIC160Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_129_GIC161Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_130_GIC162Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_131_GIC163Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR41 CPU_targets_spi_132_GIC164Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_133_GIC165Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_134_GIC166Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_135_GIC167Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR42 CPU_targets_spi_136_GIC168Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_137_GIC169Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_138_GIC170Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_139_GIC171Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR43 CPU_targets_spi_140_GIC172Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_141_GIC173Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_142_GIC174Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_143_GIC175Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR44 CPU_targets_spi_144_GIC176Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_145_GIC177Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_146_GIC178Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_147_GIC179Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR45 CPU_targets_spi_148_GIC180Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_149_GIC181Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_150_GIC182Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_151_GIC183Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR46 CPU_targets_spi_152_GIC184Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_153_GIC185Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_154_GIC186Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_155_GIC187Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR47 CPU_targets_spi_156_GIC188Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_157_GIC189Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_158_GIC190Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_159_GIC191Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR48 CPU_targets_spi_160_GIC192Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_161_GIC193Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_162_GIC194Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_163_GIC195Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR49 CPU_targets_spi_164_GIC196Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_165_GIC197Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_166_GIC198Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_167_GIC199Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR50 CPU_targets_spi_168_GIC200Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_169_GIC201Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_170_GIC202Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_171_GIC203Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR51 CPU_targets_spi_172_GIC204Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_173_GIC205Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_174_GIC206Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_175_GIC207Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDIPTR52 CPU_targets_spi_176_GIC208Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_177_GIC209Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_178_GIC210Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. CPU_targets_spi_179_GIC211Target CPU Interfaces. 0bxxxxxxx1 = CPU0. 0bxxxxxx1x = CPU1. ICDICFR0 4.3.13 Interrupt Configuration Registers, GICD_ICFGRn Purpose The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. This field identifies whether the corresponding interrupt is edge-triggered or level-sensitive, see Interrupt types on page 1-18. Attributes RW ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.7 Interrupt Configuration Registers This section describes the implementation defined features of the ICDICFR. Each bit-pair describes the interrupt configuration for an interrupt. The options for each pair depend on the interrupt type as follows: SGI The bits are read-only and a bit-pair always reads as b10. PPI The bits are read-only PPI[1] and [4]:b01 interrupt is active LOW level sensitive. PPI[0], [2],and[3]:b11 interrupt is rising-edge sensitive. SPI The LSB bit of a bit-pair is read-only and is always b1. You can program the MSB bit of the bit-pair to alter the triggering sensitivity as follows: b01 interrupt is active HIGH level sensitive b11 interrupt is rising-edge sensitive. There are 31 LSPIs, interrupts 32-62. You can configure and then lock these interrupts against more change using CFGSDISABLE. The LSPIs are present only if the SPIs are present. int_config_sgi_0The bits are read-only and a bit-pair always reads as b10. int_config_sgi_1The bits are read-only and a bit-pair always reads as b10. int_config_sgi_2The bits are read-only and a bit-pair always reads as b10. int_config_sgi_3The bits are read-only and a bit-pair always reads as b10. int_config_sgi_4The bits are read-only and a bit-pair always reads as b10. int_config_sgi_5The bits are read-only and a bit-pair always reads as b10. int_config_sgi_6The bits are read-only and a bit-pair always reads as b10. int_config_sgi_7The bits are read-only and a bit-pair always reads as b10. int_config_sgi_8The bits are read-only and a bit-pair always reads as b10. int_config_sgi_9The bits are read-only and a bit-pair always reads as b10. int_config_sgi_10The bits are read-only and a bit-pair always reads as b10. int_config_sgi_11The bits are read-only and a bit-pair always reads as b10. int_config_sgi_12The bits are read-only and a bit-pair always reads as b10. int_config_sgi_13The bits are read-only and a bit-pair always reads as b10. int_config_sgi_14The bits are read-only and a bit-pair always reads as b10. int_config_sgi_15The bits are read-only and a bit-pair always reads as b10. ICDICFR1 int_config_ppi_0The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_1The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_2The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_3The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_4The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_5The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_6The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_7The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_8The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_9The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_10The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. int_config_ppi_11_GIC27The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. int_config_ppi_12_GIC28The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. int_config_ppi_13_GIC29The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. int_config_ppi_14_GIC30The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. int_config_ppi_15_GIC31The bits are read-only. b01 = active LOW level sensitive. b11 = rising-edge sensitive. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICDICFR2 int_config_spi_0_GIC32The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_1_GIC33The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_2_GIC34The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_3_GIC35The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_4_GIC36The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_5_GIC37The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_6_GIC38The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_7_GIC39The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_8_GIC40The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_9_GIC41The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_10_GIC42The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_11_GIC43The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_12_GIC44The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_13_GIC45The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_14_GIC46The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_15_GIC47The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR3 int_config_spi_16_GIC48The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_17_GIC49The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_18_GIC50The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_19_GIC51The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_20_GIC52The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_21_GIC53The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_22_GIC54The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_23_GIC55The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_24_GIC56The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_25_GIC57The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_26_GIC58The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_27_GIC59The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_28_GIC60The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_29_GIC61The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_30_GIC62The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_31_GIC63The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR4 int_config_spi_32_GIC64The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_33_GIC65The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_34_GIC66The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_35_GIC67The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_36_GIC68The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_37_GIC69The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_38_GIC70The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_39_GIC71The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_40_GIC72The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_41_GIC73The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_42_GIC74The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_43_GIC75The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_44_GIC76The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_45_GIC77The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_46_GIC78The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_47_GIC79The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR5 int_config_spi_48_GIC80The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_49_GIC81The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_50_GIC82The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_51_GIC83The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_52_GIC84The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_53_GIC85The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_54_GIC86The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_55_GIC87The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_56_GIC88The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_57_GIC89The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_58_GIC90The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_59_GIC91The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_60_GIC92The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_61_GIC93The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_62_GIC94The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_63_GIC95The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR6 int_config_spi_64_GIC96The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_65_GIC97The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_66_GIC98The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_67_GIC99The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_68_GIC100The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_69_GIC101The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_70_GIC102The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_71_GIC103The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_72_GIC104The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_73_GIC105The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_74_GIC106The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_75_GIC107The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_76_GIC108The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_77_GIC109The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_78_GIC110The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_79_GIC111The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR7 int_config_spi_80_GIC112The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_81_GIC113The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_82_GIC114The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_83_GIC115The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_84_GIC116The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_85_GIC117The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_86_GIC118The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_87_GIC119The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_88_GIC120The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_89_GIC121The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_90_GIC122The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_91_GIC123The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_92_GIC124The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_93_GIC125The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_94_GIC126The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_95_GIC127The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR8 int_config_spi_96_GIC128The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_97_GIC129The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_98_GIC130The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_99_GIC131The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_100_GIC132The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_101_GIC133The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_102_GIC134The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_103_GIC135The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_104_GIC136The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_105_GIC137The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_106_GIC138The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_107_GIC139The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_108_GIC140The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_109_GIC141The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_110_GIC142The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_111_GIC143The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR9 int_config_spi_112_GIC144The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_113_GIC145The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_114_GIC146The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_115_GIC147The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_116_GIC148The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_117_GIC149The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_118_GIC150The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_119_GIC151The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_120_GIC152The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_121_GIC153The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_122_GIC154The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_123_GIC155The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_124_GIC156The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_125_GIC157The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_126_GIC158The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_127_GIC159The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR10 int_config_spi_128_GIC160The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_129_GIC161The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_130_GIC162The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_131_GIC163The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_132_GIC164The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_133_GIC165The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_134_GIC166The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_135_GIC167The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_136_GIC168The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_137_GIC169The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_138_GIC170The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_139_GIC171The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_140_GIC172The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_141_GIC173The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_142_GIC174The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_143_GIC175The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR11 int_config_spi_144_GIC176The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_145_GIC177The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_146_GIC178The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_147_GIC179The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_148_GIC180The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_149_GIC181The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_150_GIC182The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_151_GIC183The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_152_GIC184The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_153_GIC185The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_154_GIC186The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_155_GIC187The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_156_GIC188The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_157_GIC189The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_158_GIC190The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_159_GIC191The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR12 int_config_spi_160_GIC192The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_161_GIC193The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_162_GIC194The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_163_GIC195The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_164_GIC196The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_165_GIC197The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_166_GIC198The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_167_GIC199The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_168_GIC200The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_169_GIC201The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_170_GIC202The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_171_GIC203The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_172_GIC204The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_173_GIC205The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_174_GIC206The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_175_GIC207The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICDICFR13 int_config_spi_176_GIC208The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_177_GIC209The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_178_GIC210The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. int_config_spi_179_GIC211The LSB bit of a bit-pair is read-only and is always b1. b01 = active HIGH level sensitive. b11 = rising-edge sensitive. ICPPISR PPI Status Register IMPLEMENTATION DEFINED registers Attributes RO ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.8 PPI Status Register The ICPPISR characteristics are: Purpose Enables a Cortex-A9 processor to access the status of the inputs on the distributor: * PPI(4) is for nIRQ<n> * PPI(3) is for watchdog interrupts * PPI(2) is for private timer interrupts * PPI(1) is for nFIQ<n> * PPI(0) is for the global timer. Usage constraints A Cortex-A9 processor can only read the status of its own PPI and therefore cannot read the status of PPI for other Cortex-A9 processors. Configurations Available in all Cortex-A9 MPCore configurations. ppi_status_00 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_10 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_20 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_30 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_40 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_50 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_60 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_70 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_80 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_90 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_100 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ppi_status_11_GIC270 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ---- Cortex-A9 MPCore Technical Reference Manual ---- Global timer, PPI(0) The global timer uses ID27. ppi_status_12_GIC280 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nFIQ pin, PPI(1) In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28. ppi_status_13_GIC290 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ---- Cortex-A9 MPCore Technical Reference Manual ---- Private timer, PPI(2) Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29. ppi_status_14_GIC300 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ---- Cortex-A9 MPCore Technical Reference Manual ---- Watchdog timers, PPI(3) Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30. ppi_status_15_GIC310 = ppi[x] is LOW, 1 = ppi[x] is HIGH. ---- Cortex-A9 MPCore Technical Reference Manual ---- A legacy nIRQ pin, PPI(4) In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31. ICSPISR0 SPI Status Registers (0: SPI0~31 (GIC#32~63)) IMPLEMENTATION DEFINED registers Attributes RO ---- Generic Interrupt Controller (PL390) Technical Reference Manual ---- 3.2.13 SPI Status Registers The spi Register characteristics are: Purpose Each bit returns the status of an spi[987:0] input. Usage constraints Only accessible to processors in Secure state. Configurations This register is available in all configurations of the GIC. ---- Cortex-A9 MPCore Technical Reference Manual ---- 3.3.9 SPI Status Registers The ICSPISRn characteristics are: Purpose Enables a Cortex-A9 processor to access the status of IRQS[N:0] inputs on the distributor. Usage constraints There are no usage constraints. Configurations Available in all Cortex-A9 MPCore configurations. spi_status_0_GIC320 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_1_GIC330 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_2_GIC340 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_3_GIC350 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_4_GIC360 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_5_GIC370 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_6_GIC380 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_7_GIC390 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_8_GIC400 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_9_GIC410 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_10_GIC420 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_11_GIC430 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_12_GIC440 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_13_GIC450 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_14_GIC460 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_15_GIC470 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_16_GIC480 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_17_GIC490 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_18_GIC500 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_19_GIC510 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_20_GIC520 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_21_GIC530 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_22_GIC540 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_23_GIC550 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_24_GIC560 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_25_GIC570 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_26_GIC580 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_27_GIC590 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_28_GIC600 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_29_GIC610 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_30_GIC620 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_31_GIC630 = spi[x] is LOW, 1 = spi[x] is HIGH. ICSPISR1 SPI Status Registers (1: SPI32~63 (GIC#64~95)) spi_status_32_GIC640 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_33_GIC650 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_34_GIC660 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_35_GIC670 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_36_GIC680 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_37_GIC690 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_38_GIC700 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_39_GIC710 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_40_GIC720 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_41_GIC730 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_42_GIC740 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_43_GIC750 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_44_GIC760 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_45_GIC770 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_46_GIC780 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_47_GIC790 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_48_GIC800 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_49_GIC810 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_50_GIC820 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_51_GIC830 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_52_GIC840 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_53_GIC850 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_54_GIC860 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_55_GIC870 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_56_GIC880 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_57_GIC890 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_58_GIC900 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_59_GIC910 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_60_GIC920 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_61_GIC930 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_62_GIC940 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_63_GIC950 = spi[x] is LOW, 1 = spi[x] is HIGH. ICSPISR2 SPI Status Registers (2: SPI64~95 (GIC#96~127)) spi_status_64_GIC960 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_65_GIC970 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_66_GIC980 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_67_GIC990 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_68_GIC1000 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_69_GIC1010 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_70_GIC1020 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_71_GIC1030 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_72_GIC1040 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_73_GIC1050 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_74_GIC1060 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_75_GIC1070 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_76_GIC1080 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_77_GIC1090 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_78_GIC1100 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_79_GIC1110 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_80_GIC1120 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_81_GIC1130 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_82_GIC1140 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_83_GIC1150 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_84_GIC1160 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_85_GIC1170 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_86_GIC1180 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_87_GIC1190 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_88_GIC1200 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_89_GIC1210 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_90_GIC1220 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_91_GIC1230 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_92_GIC1240 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_93_GIC1250 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_94_GIC1260 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_95_GIC1270 = spi[x] is LOW, 1 = spi[x] is HIGH. ICSPISR3 SPI Status Registers (3: SPI96~127 (GIC#128~159)) spi_status_96_GIC1280 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_97_GIC1290 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_98_GIC1300 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_99_GIC1310 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_100_GIC1320 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_101_GIC1330 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_102_GIC1340 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_103_GIC1350 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_104_GIC1360 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_105_GIC1370 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_106_GIC1380 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_107_GIC1390 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_108_GIC1400 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_109_GIC1410 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_110_GIC1420 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_111_GIC1430 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_112_GIC1440 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_113_GIC1450 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_114_GIC1460 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_115_GIC1470 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_116_GIC1480 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_117_GIC1490 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_118_GIC1500 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_119_GIC1510 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_120_GIC1520 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_121_GIC1530 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_122_GIC1540 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_123_GIC1550 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_124_GIC1560 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_125_GIC1570 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_126_GIC1580 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_127_GIC1590 = spi[x] is LOW, 1 = spi[x] is HIGH. ICSPISR4 SPI Status Registers (4: SPI128~159 (GIC#160~191)) spi_status_128_GIC1600 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_129_GIC1610 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_130_GIC1620 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_131_GIC1630 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_132_GIC1640 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_133_GIC1650 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_134_GIC1660 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_135_GIC1670 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_136_GIC1680 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_137_GIC1690 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_138_GIC1700 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_139_GIC1710 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_140_GIC1720 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_141_GIC1730 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_142_GIC1740 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_143_GIC1750 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_144_GIC1760 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_145_GIC1770 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_146_GIC1780 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_147_GIC1790 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_148_GIC1800 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_149_GIC1810 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_150_GIC1820 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_151_GIC1830 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_152_GIC1840 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_153_GIC1850 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_154_GIC1860 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_155_GIC1870 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_156_GIC1880 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_157_GIC1890 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_158_GIC1900 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_159_GIC1910 = spi[x] is LOW, 1 = spi[x] is HIGH. ICSPISR5 SPI Status Registers (5: SPI160~179 (GIC#192~211)) spi_status_160_GIC1920 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_161_GIC1930 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_162_GIC1940 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_163_GIC1950 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_164_GIC1960 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_165_GIC1970 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_166_GIC1980 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_167_GIC1990 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_168_GIC2000 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_169_GIC2010 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_170_GIC2020 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_171_GIC2030 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_172_GIC2040 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_173_GIC2050 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_174_GIC2060 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_175_GIC2070 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_176_GIC2080 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_177_GIC2090 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_178_GIC2100 = spi[x] is LOW, 1 = spi[x] is HIGH. spi_status_179_GIC2110 = spi[x] is LOW, 1 = spi[x] is HIGH. ICDSGIR Software Generated Interrupt Register 4.3.15 Software Generated Interrupt Register, GICD_SGIR The GICD_SGIR characteristics are: Purpose Controls the generation of SGIs. Usage constraints It is IMPLEMENTATION DEFINED whether the GICD_SGIR has any effect when the forwarding of interrupts by Distributor is disabled by the GICD_CTLR settings. Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions this register is Common. The NSATT field, bit [15], is implemented only if the GIC implements the Security Extensions. Attributes WO TargetListFilter Determines how the distributor must process the requested SGI: 0b00 = Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda. 0b01 = Forward the interrupt to all CPU interfaces except that of the processor that requested the interrupt. 0b10 = Forward the interrupt only to the CPU interface of the processor that requested the interrupt. 0b11 = Reserved. CPUTargetList When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the interrupt. Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface. If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface. NSATT Implemented only if the GIC includes the Security Extensions. Specifies the required security value of the SGI: 0 = Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface. 1 = Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if the SGI is configured as Group 1 on that interface. This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write. See SGI generation when the GIC implements the Security Extensions for more information. -------- Note -------- If GIC does not implement the Security Extensions, this field is reserved. ---------------------- SGIINTID The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. ICPIDR0 Peripheral ID0 register ICPIDR1 Peripheral ID1 register ICPIDR2 Peripheral ID2 register ICPIDR3 Peripheral ID3 register ICPIDR4 Peripheral ID4 register ICPIDR5 Peripheral ID5 register ICPIDR6 Peripheral ID6 register ICPIDR7 Peripheral ID7 register ICCIDR0 Component ID0 register ICCIDR1 Component ID1 register ICCIDR2 Component ID2 register ICCIDR3 Component ID3 register