/*
 * SPItoFPGAOperation.h
 *
 * Copyright (C) 2024 MACNICA,Inc. All Rights Reserved.
 *  This software is licensed "AS IS".
 *  Please perform use of this software by a user's own responsibility and expense.
 *  It cannot guarantee in the maker side about the damage which occurred
 *  by the ab-ility not to use or use this software, and all damage that occurred secondarily.
 *  Created on: 2024/02/26
 *      Author: 12088
 */

#include "SPItoFPGAOperation.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/*******************************************************************************
 * Prototypes
 ******************************************************************************/

/*******************************************************************************
 * Variables
 ******************************************************************************/
#define BUFFER_SIZE (96)
static uint8_t srcBuff[BUFFER_SIZE];
static uint8_t destBuff[BUFFER_SIZE];
size_t txCount    = 0xFFU;

/*******************************************************************************
 * Code
 ******************************************************************************/
void SPIM_INIT(void)
{
    spi_master_config_t userConfig = {0};
    uint32_t srcFreq               = 0;
//    uint32_t i                     = 0;
//    uint32_t err                   = 0;
//    spi_transfer_t xfer            = {0};

    /*
     * userConfig.enableLoopback = false;
     * userConfig.enableMaster = true;
     * userConfig.polarity = kSPI_ClockPolarityActiveHigh;
     * userConfig.phase = kSPI_ClockPhaseFirstEdge;
     * userConfig.direction = kSPI_MsbFirst;
     * userConfig.baudRate_Bps = 500000U;
     */
    SPI_MasterGetDefaultConfig(&userConfig);

    srcFreq            = EXAMPLE_SPI_MASTER_CLK_FREQ;
    /* SPI Agent to Avalon Host Bridge Core supports the Motorola SPI Protocol, using the
     * SPI clock phase bit, CPHA = 1, and SPI clock polarity bit, CPOL = 0 mode.*/
    userConfig.phase    = kSPI_ClockPhaseSecondEdge;	/* 1 */
    userConfig.polarity = kSPI_ClockPolarityActiveHigh;	/* 0 */
    userConfig.sselNum = (spi_ssel_t)EXAMPLE_SPI_SSEL;
    userConfig.sselPol = (spi_spol_t)EXAMPLE_SPI_SPOL;
    SPI_MasterInit(EXAMPLE_SPI_MASTER, &userConfig, srcFreq);

    return;
}

#if 1
int spi_command(unsigned int base, unsigned int slave, unsigned int write_length, const unsigned char * write_data,
                 unsigned int read_length, unsigned char * read_data, unsigned int flags)
{
    spi_transfer_t xfer = {0};

	//----------------------------------------------------------------------------------------
    // alt_avalon_spi_command() is Altera's SPI Driver function. If you are using another SPI
	// driver, replace this with your own SPI Driver functions.
    //----------------------------------------------------------------------------------------
	//alt_avalon_spi_command(base,slave,write_length,write_data,read_length,read_data,flags);
    /*Start Transfer*/
    xfer.txData      = (uint8_t*)write_data;
    xfer.rxData      = (uint8_t*)read_data;
    xfer.dataSize    = write_length + read_length;
    xfer.configFlags = kSPI_FrameAssert;
    SPI_MasterTransferBlocking((SPI_Type*)base, &xfer);

	return 0;
}
#endif

status_t fpga_spi_bridge_write(uint32_t target_addr, uint8_t *data, size_t txSize)
{
	// ------------------------------------------------------
	// Perform an Avalon-MM write transaction of burst_length
	// bytes to the specified address.
	// ------------------------------------------------------
	//unsigned char transaction_channel_write (unsigned int address,
	//									unsigned int burst_length,
	//									unsigned char* data_buffer,
	//									unsigned char sequential);

	return transaction_channel_write(target_addr, txSize, data, NON_INCREMENT_ADDRESS);
}

status_t fpga_spi_bridge_sequential_write(uint32_t target_addr, uint8_t *data, size_t txSize)
{
	// ------------------------------------------------------
	// Perform an Avalon-MM write transaction of burst_length
	// bytes to the specified address.
	// ------------------------------------------------------
	//unsigned char transaction_channel_write (unsigned int address,
	//									unsigned int burst_length,
	//									unsigned char* data_buffer,
	//									unsigned char sequential);

	return transaction_channel_write(target_addr, txSize, data, INCREMENT_ADDRESS);
}

status_t fpga_spi_bridge_read(uint32_t target_addr, uint8_t *data, size_t rxSize)
{
	// -------------------------------------------------------
	// Perform an Avalon-MM read transaction of burst_length
	// bytes to the specified address.
	// -------------------------------------------------------
	//unsigned char transaction_channel_read  (unsigned int address,
	//									unsigned int burst_length,
	//									unsigned char* data_buffer,
	//									unsigned char sequential);

	return transaction_channel_read(target_addr, rxSize, data, NON_INCREMENT_ADDRESS);
}

status_t fpga_spi_bridge_sequential_read(uint32_t target_addr, uint8_t *data, size_t rxSize)
{
	// -------------------------------------------------------
	// Perform an Avalon-MM read transaction of burst_length
	// bytes to the specified address.
	// -------------------------------------------------------
	//unsigned char transaction_channel_read  (unsigned int address,
	//									unsigned int burst_length,
	//									unsigned char* data_buffer,
	//									unsigned char sequential);

	return transaction_channel_read(target_addr, rxSize, data, INCREMENT_ADDRESS);
}
