Example of DDR4 Random Address Access Efficiency Measurement on Agilex® 7 FPGA

Description.

This is an example of random address access to DDR4 from Agilex® 7 FPGA & SoC. 
IP option settings were changed to see the change in execution efficiency.

Contents

1. EMIF IP efficiency improvement options

2. Tested on actual device

3. Actual test results

4. Summary