1. Introduction.
The memory map for accessing the DDR (hereinafter called HPS DDR) on the HPS side of the Stratix® 10 FPGA and the Agilex™ 7 FPGA from the FPGA Fabric and from the MPU is provided. If you do not understand the Memory Map when accessing the HPS DDR, you may not be able to access the expected address. This article introduces the recommended Memory Map, and we hope it will be helpful when accessing the HPS DDR.
[Figure 1] Access path from FPGA Fabric and MPU to HPS DDR
* Excerpt from Agilex™ 7 Hard Processor System Technical Reference Manual
Point: The MPFE is accessed directly from the FPGA Fabric side and through the Cache Coherency
Unit from the MPU.
2. Access to HPS DDR
HPS DDR has a Memory Map.
In order to write to the intended address, it is necessary to understand the correct Memory Map.
This chapter describes the recommended memory map for access from the FPGA Fabric and MPU.
2-1. MPU Address Map
First of all, we introduce the MPU address map as a preparation. In the next section, we will introduce the HPS DDR Memory Map, but it is better to see the MPU Address Map in advance so that you can compare them and understand the details.
The address map of HPS is shown in the figure below. 0~2GB space and 4~128GB space are occupied by SDRAM, and 2~4GB space is occupied by Peripherals, Bridges, etc.
[Figure 2] Hole space
* Excerpt from Agilex™ 7 Hard Processor System Technical Reference Manual
Point: SDRAM is located in the 0~2GB and 4~128GB spaces, and Peripheral and Bridge are located
in the 2~4GB space.
(This 2~4GB space is called a Hole.)
2-2. Recommended Memory Map
The figure below is a recommended memory map extracted from the document.
From left to right, it shows the size of DDR, physical address of DDR, address to be accessed from MPU, and address to be accessed from FPGA side.
[Figure 3] Recommended Memory Map
* Excerpt from Agilex™ 7 Hard Processor System Technical Reference Manual
Tip: Total DDR size -> Size of DDR
External DDR address range -> Physical address of DDR
Address range for MPU -> For access from MPU
Address range for FPGA(FPGA-to- HPS) -> For access from FPGA Fabric side
2-3. Example of access when the size of HPS DDR is 8GB
The following figure shows an excerpt from the Memory Map when the size of HPS DDR is 8GB.
[Figure 4] Memory Map in case of 8GB
* Excerpt from Agilex™ 7 Hard Processor System Technical Reference Manual
The memory map for 8GB accessed from the MPU and FPGA Fabric side is the same.
Therefore, the image of both is as shown in the figure below.
[Figure 5] Memory Map diagram in the case of 8GB
Point: Access to the Hole (2~4GB space) is also possible by following the recommended
Memory Map.
Some examples of access are shown below.
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-
-
- To access 0x00_0000_0000 of HPS DDR (first address of 2GB area of 8GB):
-> Access 0x00_0000_0000 - To access 0x00_8000_0000 of HPS DDR (first address of 6GB area of 8GB):
-> access 0x10_8000_0000
- To access 0x00_0000_0000 of HPS DDR (first address of 2GB area of 8GB):
-
-
3. Related information (ECC error when accessing HPS DDR)
When accessing HPS DDR from FPGA, an ECC error may occur if the address is different from the memory map.
Please refer to the following information published by the manufacturer.
4. Conclusion
This article introduced the Memory Map for Stratix® 10 FPGA / Agilex™ 7 FPGA.
By following the recommended memory map, it is possible to access hole space that cannot be accessed directly. We hope this article is useful for your design.