1 . Overview (including IP & Configuration)
In this article, we will discuss the structure of Booting Nios® V processor from On-Chip Memory (here in after referred to as On-Chip RAM). this article describes the minimum IP parameters and BSP Editor settings required to boot the Nios® V processor from On-Chip RAM, and how to generate an initial value file for On-Chip RAM.
In the configuration described in this article, the software file is stored in On Chip RAM as the initial value file. The advantage of this configuration is that by storing the initial value file in On Chip RAM, the Nios® V processor as soon as the FPGA power is turned on.
Although there are some differences in operation, most of the necessary settings are the same as in Nios® II. For this reason, please refer to the following article on setting up the Boot method for Nios® II for a better understanding.
Reference: Types of Nios® II Boot and how to configure each Boot Option - (In Japanese)
The minimum IP requirements are as follows Quartus® Prime Pro Edition software version 22.4
- Nios® V/m Processor Intel® FPGA IP
- On-Chip Memory (RAM or ROM) Intel® FPGA IP
Figure 1 is Platform Designer configuration
Figure 1. Platform Designer configuration
In this article, JTAG_UART IP is implemented for console output, but please note that it is not required.
The names of the implemented IPs are set as follows to improve visibility.
- Clock Bridge Intel® FPGA IP : Clock
- Reset Bridge Intel® FPGA IP : Reset
- Nios® V/m Processor Intel® FPGA IP : NiosV
- On-Chip Memory (RAM or ROM) Intel® FPGA IP : OCRAM
- JTAG UART Intel® FPGA IP : JTAG_UART
The IP required for this Boot configuration - the Nios® V processor, On-chip RAM - are described in the next section.
1-1. Nios® V/m Processor Intel® FPGA IP
"Enable Debug" and "Enable Reset from Debug Module" under "Debug" should be enabled as shown in Figure 2, and "OCRAM.s1" should be set to Reset Agent under Vectors.
Figure 2. Nios® V/m Processor Parameter Settings
Note:
When selecting the Reset Agent: pull-down menu, the "OCRAM.s1" port may not appear. In this case, select a different port and then open the pull-down menu again.
1-2. On-Chip Memory (RAM or ROM) Intel® FPGA IP
Set the Total memory size required for software execution as shown in Figure 3, and set the Memory Initialization to specify the initial value file to be registered in the On-Chip RAM.
Figure 3. On Chip RAM Parameter Settings
Nios® II processors, the initial value file can be registered using memint.qip. but Nios® V processors, the RiscFree IDE does not have a command to generate meminit.qip, so you must also check the " Enable non-default initialization file" check box as shown in Figure 3 and register the <any name>.hex path as shown in Figure 3.
In this article, the settings are as follows.
- Total memory size: 51200 Bytes
- User created initialization file: ram.hex
For details on how to create a HEX file, refer to "3-1. Generate HEX file"
1-3. Quartus® Prime Settings
Open Assignment tab -> Device -> Device and Pin Options -> Configuration.
- Configuration scheme: Sets the FPGA configuration scheme.
- Active serial clock source: Sets the clock frequency when configuring the FPGA.
Figure 4. Quartus® Prime Device and Pin Options
2. BSP Editor Settings
Start the BSP Editor from Platform Designer and create Setting.bsp file. If you do not know how to create the file, please refer to the following link.
For instructions on how to start the BSP Editor, please refer to the Nios® II processor and the Nios® V processors, but the settings are the same. Below are the settings for Linker Script and hal.linker.
To set the Linker Script, select the BSP Linker Script tab and set the sections other than .entry to "OCRAM" as shown in Figure 5 .
Figure 5. BSP Linker Script Settings
To set hal.linker, go to Settings -> Advanced -> hal in the Main tab and check the hal.linker option as shown in Figure 6.
- allow_code_at_reset
- enable_at_load
- enable_alt_load_copy_rwdata
Figure 6. hal.linker settings
This is all about the settings in the BSP Editor.
In the next section, we will introduce how to generate the HEX file and Programming file to be registered in On Chip RAM.
3. How to Generate Programming File
After compiling the software and generating the ELF file, generate the HEX file to be registered as the initial values of On Chip RAM.
Please refer to the following article for the procedure to generate the ELF file.
Reference: Nios® V Project Development Procedure Using Ashling* RiscFree* IDE > 4-4. Starting up RiscFree* IDE
3-1. Generate HEX file
After the ELF file generation is complete, click on the Nios® V Command shell and change the current directory to the project you created.
After moving to the current directory, enter the following command to create a HEX file.
$ elf2hex software/app/build/Debug/<generated ELF file>.elf -o <any name>.hex -b <base address of On Chip RAM> -w <data width of On Chip RAM> -e <end address of On Chip RAM>
Execution example
$ elf2hex software/app/build/Debug/hello.elf -o ram.hex -b 0x00010000 -w 32 -e 0x0001c7ff
<any name>.hex will be generated and should be registered to On-Chip RAM according to the procedure described in "1-2. On-Chip Memory (RAM or ROM) Intel® FPGA IP".
This is all that is required for On-Chip RAM Boot of the Nios® V processor.
3-2. POF File and JIC File
When Booting from On Chip RAM, the software information is included in the SOF file because the software file is registered as the initial value file.
Therefore, the software information can be reflected in the Programming file by generating POF file and JIC file from the SOF file as usual.
For instructions on how to incorporate the updated HEX file into the SOF file without fully compiling Quartus® Prime, please refer to this document.
Reference: Nios® II - Booting from On-Chip Memory - (In Japanese)
Conclusion
For more information on Nios® V processors, please refer to the manufacturer's page below.