1. introduction
This article introduces an example of write/read operation with Nios® V connected to DDR4 memory.
The following development kits are used to verify the operation.
Intel Agilex® 7 FPGA F-Series Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)
The DDR4 memory capacity connected to the FPGA on the development kit is 8GB DIMMs and 2GB components for a total of 10GB.
Nios® V has only 4GB address space, which is not enough address space.
Therefore, in this article, we used Address Span Extender to extend the address space and built a system with 2GB of Nios® V access area.
Please refer to the following article for more information on Address Span Extender.
Reference material: How to use Address Span Extender to extend the address space of Master such as Nios® II
2. FPGA Design
Figure 1 shows a block diagram between Nios® V and DDR4 memory. Since the user side of the External Memory Interface (EMIF) IP and the Address Span Extender have different clock domains, a Clock Crossing Bridge was inserted. Although the tool automatically inserts the bridge without inserting it in the design, we inserted it explicitly this time.
The entire FPGA design is based on this block diagram, which was added to the sample design in the following article.
References: Ashling* RiscFree* IDE for Nios®V Project Development
Figure 1: Block Diagram
The following connections were made using Platform Designer.
Figure 2: Platform Designer Screen
The DDR4 memory area to be accessed from Nios® V is set in the control register of the Address Span Extender. The address of area 1 is set to 0x0_0000_0000, and the address of area 5 is set to 0x2_0000_0000.
Figure 3: Address Map
Program for Nios® V operation
The program for Nios® V operation is shown below.
First, the DDR4 memory area to be accessed is set in the Address Span Extender control register, and then DDR4 memory is accessed.
Figure 4: Operation Program
Please refer to the following article for the Nios® V operation procedure.
Reference material: Ashling* RiscFree* IDE for Nios®V Project Development
Result of Operation Check on Actual Device
In the operation check on the actual device, it was confirmed that each area was accessed as expected using SignalTap.
Figure 5: Access to addr = 0x0 of DIMM (area ① in Figure 1)
Figure 6: Access to addr = 0x7FFF_FFFF of DIMM (area (4) in Figure 1)
Figure 7: Access to addr = 0x0 in components (area ⑤ in Figure 1)
Figure 8: Address of components = 0x1FFF_FFFF (area ⑤ in Figure 1)
5. Conclusion
In this article, we introduced a write/read example using Address Span Extender to extend the address space by connecting Nios® V to DDR4 memory. The design is attached for your reference.