Nios® V Boot Option ~ Generic Serial Flash Interface ~

1. Introduction

This article describes how to Boot Nios^® V from Flash ROM (Quad SPI Flash) with Boot Copier or XIP (Execute in Place) using Generic Serial Flash Interface Intel^® FPGA IP (GSFI). The following is an introduction to the GSFI method.

For more information on GSFI, please refer to the User Guide below.

Reference: Generic Serial Flash Interface Intel® FPGA IP User Guide

Reference: Nios® V Processor BootingNios® V Processor Booting from Configuration QSPI Flash

For the difference between XIP and Boot Copier, please refer to the following article on Nios^® II, as the configuration is the same.

Reference: Types of Nios^® II Boot and how to configure each Boot Option - (In Japanese)

2. Overview

QSPI Boot with Nios^® V uses GSFI as Serial Flash controller, which is the latest Serial Flash Controller from Intel^®, GSFI is the latest Serial Flash Controller from Intel^® and can support all Flash ROMs by setting the parameters.

However, there are two points to note when using GSFI as the Serial Flash Controller.

• GSFI parameters must be set according to I/O Mode (Standard/QUAD) and Flash ROM specifications.
• HEX file must be generated by command because mem_init of Nios^® II SBT is not supported.

For more information on "Relationship between Boot and Flash Controller" and "Basic Concept of Booting", please refer to the following article which describes the conventional Nios^® II Boot method and Nios^® V. There is no significant difference between Nios^® V and Nios^® II.

Reference: Embedded Peripherals IP - Comparison of Various Flash Controllers > 3. Relationship with Nios^® II Boot - (In Japanese)

Reference: Nios^® II Boot Option ~ EPCQ Flash ~ (using AS IF) - (In Japanese)

Reference: Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF) - (In Japanese)

3. Quartus^® Prime Settings and Platform Designer System Configuration

3-1. Quartus^® Prime Configuration

When storing the Nios^® V software in the Configuration ROM, the GSFI parameter settings must match the Quartus^® Prime configuration scheme settings.

Open Assignments tab ⇒ Device ⇒ Device and Pin Options ⇒ Configuration and set the items shown in Figure 1.

• In case of Standard mode: Active Serial x 1 (can use Configuration Device)
• In case of Quad mode: Active Serial x 4 (can use Configuration Device)

Figure 1. Device and Pin Options for Quartus^® Prime

When a JIC or POF file is written to the Configuration ROM, the value of the dummy cycle written to the Nonvolatile Configuration Register changes depending on the combination of Flash ROM capacity and AS ×1 / AS ×4.

Also, if the GSFI parameter settings do not match the Configuration scheme settings, the device cannot be properly booted.

The method of setting GSFI parameters is described in the chapter "5. Setting of GSFI parameters".

Refer to the information below to check the dummy cycle values and adjust the GSFI parameters.

Reference: Intel Supported Third Party Configuration Devices

Reference: Why does Active Serial (AS) configuration fail in Stratix V, Arria V, and Cyclone V devices when using an EPCQ device which is programmed in an embedded

3-2. Platform Designer System Configuration

Platform Designer configuration can be realized with the same configuration as in the following article, except for GSFI.

Reference: Nios® V Boot Option ~ On Chip RAM (XIP)

Figure 2. Platfom Designer System Diagram

• • Clock Bridge Intel^® FPGA IP: Clock
  • Reset Bridge Intel^® FPGA IP: Reset
  • Nios^® V/m Processor Intel^® FPGA IP：NiosV
  • On-Chip Memory (RAM or ROM) Intel^® FPGA IP：OCRAM
  • JTAG UART Intel^® FPGA IP：JTAG_UART
  • Generic Seial Flash Interface Intel^® FPGA IP：GSFI

As well as Boot from On Chip RAM, JTAG_UART is implemented for console output for operation check, so it is not required for this configuration.

As for connections, it is necessary to connect Nios^® V's "instruction_manager" to the "s1" port of On Chip RAM as the execution memory of Nios^® V and the "avl_mem" port of GSFI as the data storage destination.

For other connections, connect the "data_manager" of Nios^® V to the Avalon-MM slave of the IP that needs to be controlled by Nios^® V as shown in Figure 2. 

4. Setting of Nios^® V parameters

In setting up the parameters required for GSFI Boot of Nios^® V, set the address that Nios^® V will refer to after Reset is released.
The file to be programmed into the Flash ROM is created by converting the configuration data and Nios^® V data into a JIC file, which is then saved as a file on the Nios^® V's hard disk, The user can arbitrarily set where to place the Nios^® V data. Therefore, the start address of the Nios^® V data (.hex) to be referenced after Reset is released must be set to the Reset Offset of Nios^® V.

4-1. Various Setting Items of Nios^® V

First, enable "Enable Debug" and "Enable Reset From Debug Module" under Debug as shown in Figure 3.

Then, set "GSFI.avl_mem" to Reset Agent under Vector. At this point, there is no problem with the default value (0x00000000) for Reset Offset under Vector.

Figure 3. Parameters of Nios^® V

4-2. How to set Reset Offset

Since the Reset Offset must be set to the start address of the HEX file, it is necessary to check the end address of the generated SOF file.

The end address can be calculated from the file size, but it is also possible to create a JIC file from the generated SOF file and check the end address from the map file generated at that time.

The method for generating a JIC file is described in section "7-3. How to Generate JIC File".

In Figure 4, 0x00b00000 is set to Reset Offset because it is necessary to set the start address of the HEX file to an address larger than the end address of the SOF file.

Figure 4. How to set Reset Offset

This is the end of the parameter settings for Nios^® V. 

5. Setting of GSFI parameters

When setting GSFI parameters in Platform Designer, the Default Settings item in Figure 5, which is normally hidden under the Show/Hide Hidden Parameters option, can be used to set the initial values after IP startup. After power-on, Nios^® V will start up. After power-on, the Default Settings item must be set according to each Flash device in order for Nios^® V to boot.

Please refer to the following article for details on how to display the Default Settings and the values to be set when using each Flash device.

Reference: Embedded Peripherals IP - Generic Serial Flash Interface Sample - (In Japanese)

Figure 5. Default Settings of GSFI Default Settings

6. BSP Editor Settings

This chapter introduces the settings for each Boot method of Nios^® V. After executing Generate HDL in Platform Designer, use the BSP Editor to configure the settings.

Please refer to the following article for details on how to start the BSP Editor.

Reference: Ashling* RiscFree* IDE for Nios® V Project Development > 4-2. Bsp project creation

6-1. Configuration of Nios^® V for Boot Copier Booting 

Boot Copier is a Boot method to run Nios^® V by setting all Linker Section to RAM (On Chip RAM or external RAM) and extracting necessary data from Flash ROM to RAM by Boot Loader called Boot Copier.

Since the Boot Loader expands all necessary data to RAM, all settings in hal.linker should be turned off.

Figure 6 shows an example.

Figure 6. BSP Editor Settings in Boot Copier Configuration

6-2. Configuration of Nios^® V for XIP Booting

XIP (Execute in Place) is a Boot method in which the .text area of the Linker Section is allocated to the Flash Controller to run Nios^® V on Flash ROM.

If sections other than .text are set to be stored in RAM, all settings in hal.linker must be enabled in order to deploy them in RAM during Boot.

NOTES:
The .rwdata section, .heap section, and .stack section (read/write data area) must be placed in RAM even when used in an XIP configuration because they involve Flash rewriting.

Figure 7 shows an example.

Figure 7. Nios^® V SBT BSP Editor settings in XIP

Note:

If Exception vector memory is set to GSFI, turn off "enable_alt_load_copy_exceptions" from the settings in hal.linker.

Next, from the BSP Drivers tab, uncheck "Enable" for intel_generic_serial_flash_inteface_top shown in the red frame in Figure 8. This setting disables the GSFI Device Driver.

Figure 8. Nios^® V SBT BSP Driver setting in XIP

Note:
If the Device Driver of GSFI is enabled, the data read will be invalid and Boot will not be completed normally because GSFI initialization is performed by alt_sys_init() while the memory connected to GSFI is in use when Nios^® V Boot is performed.

7. How to generate Programming File

In case of Nios^® V Boot using GSFI, mem_init is not supported, so the HEX file to be stored in Flash ROM is generated by using the command in Nios^® V Command Shell.

7-1. ELF to HEX command for Boot Copier

The following is the procedure for generating a HEX file for Boot Copier.

Please note that the procedure described in this section is based on the assumption that the Nios^® V software is running in the debugger according to the following contents.

Reference: Ashling* RiscFree* IDE for Nios® V project development

1. 1. Copy the Boot Copier (.serc) file from the following path to the app folder of Nios^® V.
      <Quartus^® Prime installation directory>\niosv\components\bootloader
      When using Nios^® V/m: niosv_m_bootloader.srec
      When using Nios^® V/g: niosv_g_bootloader. srec
      
      Point: Copy the absolute path to avoid commands not working, etc.
      
      
   2. Start the Nios^® V Command Shell and set the current directory to the app folder.
   3. Execute the following commands according to the environment you are using.

Point: First, run elf2flash.exe to merge the application executable (.elf) and Boot Copier (.srec) to generate S-Record format (.srec), then convert it to Hex format (.hex) by objcopy in two steps. The two-step procedure is as follows.

Execution command

elf2flash --input <Input file name(.elf)> --output <Output file name(.srec)> --reset <Nios V Reset Address> --base <Base address of GSFI> --end <End address of GSFI> --boot <Boot Copier(.srec)>

riscv32-unknown-elf-objcopy --input-target srec --output-target ihex <Input file name(.srec)> <Output file name(.hex)>

Example of command execution

elf2flash --input app.elf --output flash.srec --reset 0x00b00000 --base 0x00000000 --end 0x00ffffff --boot niosv_m_bootloader.srec

riscv32-unknown-elf-objcopy --input-target srec --output-target ihex flash.srec app.hex

7-2. ELF to HEX command for XIP

The following is the procedure for generating a HEX file for XIP.
Please change to the Boot Copier setting, confirm that the Nios^® V software runs with Run As, and then change back to the XIP setting to generate the HEX file.

Reference: How to debug in XIP configuration - (In Japanese)

1. 1. Start the Nios^® V Command Shell and change the current directory to the app folder.
   2. Execute the following command with the following arguments according to your environment.
      
      Point: First, run elf2flash.exe to generate the application executable (.elf) in
      S-Record format (.srec), and then convert it to Hex format (.hex) by objcopy in a two-step procedure.

Execution command

elf2flash --input <Input file name(.elf)> --output <Output file name(.srec)> --reset <Nios V Reset Address> --base <Base address of GSFI> --end <End address of GSFI>

riscv32-unknown-elf-objcopy --input-target srec --output-target ihex <Input file name(.srec) > <Output file name(.hex)>

Example of command execution

elf2flash --input app.elf --output flash.srec --reset 0x00b00000 --base 0x00000000 --end 0x00ffffffff

riscv32-unknown-elf-objcopy --input-target srec --output-target ihex flash.srec app.hex

7-3. How to Generate JIC File

Generate JIC file by Convert Programming File.

When storing in the AS Interface Configuration ROM, the JIC file can be generated and written via JTAG using Quartus^® Prime Programmer.

In addition, a JIC binary file can be generated at the same time by enabling Create config data RPD in the Convert Programming File.

Please refer to the following article for details on how to generate a JIC file.

Reference: Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF) > 4-2. Generating JIC Files - (In Japanese) 

Point:
In case of XIP, Absolute addressing may not work well depending on the HEX file settings. In this case, please refer to the FAQ below.

Reference: FAQ: How can I adjust the HEX storage address with Relative Addressing in Convert Programming Files? - (In Japanese)

Conclusion

In this article, we introduced how to boot Nios^® V from Flash ROM (Quad SPI Flash) using GSFI.

For more information on Nios^® V, please refer to the manufacturer's page below.

• Nios^® V Processor Developer Center