1. Introduction
Stratix® 10 FPGAs and Agilex™ 7 FPGAs are available as SoC-type devices, but even SoC devices are not required to use HPS.
There may be cases where you only have an evaluation kit for an SoC-type device, or you may have to design with an SoC device for some reason.
This article describes how to design without HPS.
Key Points:
In Altera's SoC FPGAs (SoC type devices), a block with an Arm processor and various peripherals is called a Hard Processor System (HPS).
2. Processing when HPS is not used
This article describes the process when HPS is not used, focusing on design and pin configuration.
Each is described below.
2-1. design
There is no problem with simply not including the HPS in Platform Designer (Figure 1). Therefore, you can follow the same procedure as in normal FPGA design without being particularly conscious of the HPS.
[Figure 1] Example of Platform Designer without HPS
Point:
If your design includes HPS, you will need to incorporate a boot loader into sof/jic. However, even for SoC type devices, it is not necessary to incorporate a boot loader when the HPS is not used.
2-2. pins
Please refer to the following document for pin handling when the HPS is not used.
[Figure 2] Pin handling when HPS is not used
* Excerpt from AN 802: Stratix® 10 SoC Device Design Guidelines
Point: The
Clock pin is included in the 48 HPS Dedicated IOs. Therefore, when the HPS is not used, the Clock pin of the HPS can be left unconnected according to the processing described in the table above.
3. Conclusion
This article describes the design and pins of the Stratix® 10 FPGA and Agilex™ 7 FPGA without HPS. We hope this article has been helpful to you when you are not using the HPS.