Introduction
The last version of the development tool to support the Nios® II softcore processor from Altera (hereafter as Nios® II) was released in the winter of 2023 (Quartus® Prime Pro v23.4, Quartus® Prime Standard v23.1). After that, developers will migrate to Nios® V processors based on the RISC-V architecture (hereafter as Nios® V).
Nios® V tends to increase the logic size compared to Nios® II, and we have been asked by some customers who are considering migration to Nios® V about reducing the logic size.
This article describes how to reduce the logic size of circuits using Nios® V.
1. Logic size of Nios® V
Nios® V is available in three core types as described in the following article.
Reference: Nios® V Processor
For more information about the logic size of each core, please refer to Nios® V Processor Reference Manual for the logic size of each core.
Reference: Nios® V/c Logic Size
Reference: Logic Size of Nios® V/m (Non-pipelined)
Reference: Logic Size of Nios® V/m (Pipelined)
Reference: Logic Size of Nios® V/g
Please refer to the following link for a description of Nios® II logic sizes.
Reference: Nios® II Logic Size
Nios® V continues to improved with each tool version upgrade for the future. We recommend using the latest tools whenever possible.
2. Logic Size Reduction Methods
There are four methods for reducing logic size. These can be applied individually or in combination to reduce logic size.
1. Selecting the optimal Nios® V core
2. Disabling the pipeline stage (Nios® V/m)
3. Changing Compiler Settings in Quartus® Prime
4. Inserting a Pipeline Bridges
Each of these is described below.
2-1. Selecting the optimal Nios® V core
As mentioned above, Nios® V has three types of cores. Each core has different performance and logic size, so select the optimal core for your system.
Table 1. Logic Size Example (Agilex™ 5 in Quartus® Prime Pro v24.1)
| Nios® V/c |
Nios® V/m |
Nios® V/m |
Nios® V/g | |
| Logic Size (ALM) | 409 |
707 |
1232 |
2079 |
| Fmax (MHz) | 371 |
384 |
347 |
255 |
| DMIPS/MHz | 0.227 |
0.227 |
0.63 |
1.276 |
| CoreMark/MHz | 0.17 |
0.170 |
0.489 |
1.869 |
Logic size and maximum operating frequency (Fmax) vary depending on the device and user implementation.
Please refer to the data sheet for a rough guide and refer to the links for logic size for each core in " 1. Logic size of Nios® V ".
NOTES: Nios® V/c cores are designed to reduce logic size and do not implement the following features. Therefore, we recommend using Nios® V/m or Nios® V/g whenever possible.
- Debug Module
- Interrupt controller / Exception controller
2-2. Disabling the pipeline stage (Nios® V/m)
For Nios® V/m, you can choose whether or not to use the pipeline stages of the processor.
Nios® V/m implements 5 pipeline stages for better performance, and starting with Quartus® Prime pro v23.3 / Quartus® Prime Standard v23.1 has a new setting to turn off this pipeline stage.
The pipeline stage can be uninstalled by unchecking the Enable Pipelining in CPU checkbox as shown in the figure below.
Figure 1. Enable Pipelining check box
2-3. Changing Compiler Settings in Quartus® Prime
Logic size can be reduced by changing the Compiler Settings of Quartus® Prime to Area.
Go to Assignments -> Settings -> Compiler Settings and set the Optimization mode to Area.
Figure 2. Compiler Settings
2-4. Inserting a Pipeline Bridges
Nios® V uses the AXI4 / AXI4Lite interface, and by adding an Avalon®-MM Pipeline Bridge between Nios® V and the Avalon®-MM Slave, the interconnect to which the Pipeline Bridge is inserted can be connected to the Avalon®-MM interface. The Avalon®-MM interface is used to reduce logic size.
For more information about the Avalon®-MM Pipeline Bridge, please refer to the following
Reference: 4.1.3. Avalon®-MM Pipeline Bridge
An example implementation in a Platform Designer system is shown in the figure below.
Figure 3. Insertion of Avalon®-MM Pipeline Bridge
Conclusion
We hope this article on how to reduce the logic size of circuits using Nios® V has been helpful to you when using Nios® V.
The following articles contain information related to Nios® V. We hope you will find it useful.