Hi, I'm a trout guy.
This week, I will start the second part of "Masuo's FPGA Practice Series" !
In the first part of the series, I have introduced some red faced episodes, but from the second part of the series, I will be sending out more and more useful information for FPGA design!
In this first installment, we will introduce a design method to optimize the phase adjustment of PLL (Phase-Locked Loop). For a detailed explanation of PLL, please refer to Taro's column " PLL Frequency divider / multiplier".
1. global routing
Altera FPGAs have global routing, which is a dedicated routing area adjusted in advance so that Skew is close to "0". The best design is to implement signals with many fan-outs, such as clock and reset signals, in the global routing. Figure 1 shows the global routing architecture of the Cyclone® IV E. The number of PLLs, the number of global routings, and the routing architecture vary depending on the device, so please refer to the Handbook for the device in question. In this column, Cyclone IV E is used as an example.
Figure 1: Global Routing Architecture of Cyclone® IV E
The Cyclone IV E has PLL_1~4 at the four corners of the device. They are implemented in the global routing by pin assignment to the input clock pins (=CLK [*]); the signals that drive the PLLs are pinned to CLK [*].
2.Placement and wiring to optimize PLL phase adjustment
Even if the signals that drive the PLL are pinned to CLK [*], there are cases where the phase adjustment that is a feature of the PLL is not compensated depending on the wiring used. If wiring that does not compensate for phase adjustment is used, a critical warning (Figure 2) will occur at the Fitter.
Figure 2: Critical Warning when phase adjustment is not compensated
The Fitter automatically selects the wiring from CLK [*] based on the placement of CLK [*] and the PLL/wiring area utilization. Therefore, there is no user specification for routing. The wiring results can be seen in the PLL Summary (Figure 3) of the compilation report.
Figure 3 PLL Summary Compilation Report
In the PLL Summary of Figure 3, PLL_1 marked "Dedicated Pin" is optimized for phase adjustment (Figure 4). On the other hand, PLL_4 labeled "Global Clock" is not compensated for phase adjustment (Figure 5).
Figure 4: Diagram of PLL phase adjustment compensated wiring
Figure 5: Diagram of wiring in which PLL phase adjustment is not compensated
Wiring is not something that users can specify. However, it is possible to direct Fitter to the wiring where PLL phase adjustment is compensated (= Dedicated Pin) by devising "design" and "pin assignment".
Conclusion
The input clock signal that drives the PLL is pinned to CLK[*].
Even if pinned to CLK[*], phase adjustment, a feature of the PLL, may not be compensated in some cases depending on the wiring used.
→ The PLL with the wiring indicated as "Dedicated Pin" in the PLL Summary optimizes the phase adjustment.
→ The PLL with the wiring indicated as "Global Clock" in the PLL Summary does not compensate for the phase adjustment.
In the next article, we will show how to induce Fitter in Dedicated Pin wiring.
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