Hello. My name is Toryo and I am a pain in the ass.
I am always looking for ways to shorten the time I have to do my work.
After designing a circuit using Quartus® II, it is usual to run RTL simulation using HDL simulators such as ModelSim®.
However, to run the simulation, we need something called a test bench file.
What's a test bench?
In a nutshell, a test bench is,
- “Give an input signal to a target circuit using Verilog HDL or VHDL, and observe the output signal.
This is called a “test bench”.
Although it is located at the top level of the circuit in the project, it is not subject to logic synthesis because it is only a testbench.
However, writing the whole thing from scratch in HDL is a bit tedious, since it is necessary to set values for all input signals including clock and reset signals....
Good news for such a hassle-free person!
A kind senior who was passing by taught me a "secret trick!"
Today, I would like to introduce it to you!
All you need is a design file! (Verilog HDL or VHDL)
For tools, prepare a PC and Quartus II.
I'll use a simple design this time to show you how to cook the backstage method in an easy-to-understand way.
module sample
(
input clk, reset, output reg [3:0] count
output reg [3:0] count
);
always @ (posedge clk or negedge reset)
begin
if (!reset)
count <= 0;
else
count <= count + 1'b1; end
end
endmodule
Now, let's start cooking!
1) Start Analysis & Synthesis (Processing menu > Start) to synthesize the design at the top level. 2) In the EDA Tool Settings, select the tool to be used for simulation, the language and time scale of the generated testbench.
2) To generate a testbench, select the tool to be used for simulation, the language of the generated testbench, and the time scale in the EDA Tool Settings.
3) Execute Processing > Start > Start Test Bench Template Writer.
4) When completed, confirm that the message window displays “EDA Netlist Writer was successful.
If you have a pop-up setting for process completion, this window will appear
That's all there is to it! !
I did it faster than 3-minute cooking!
*The time required for logic synthesis and testbench generation depends on your design.
The completed testbench file is in the directory /simulation / modelsim specified in step 2, so open it in the Quartus II text editor and show off the completed file.
What a surprise! The information necessary for the test bench was extracted from the top-level design and automatically reflected in the file!
As you can see, the inputs and outputs of my design are connected to the ports, so all I have to do now is describe what the input signals should be. In other words, all you have to do is input the test pattern.
This time we only used a simple Verilog HDL file, but as long as the logic synthesis is complete, testbenches for more complex designs can also be generated. In other words, the larger the design, the easier it is!
This time-saving function is perfect for engineers who are pressed for time to meet deadlines! Let's continue to learn more about the various functions and pursue more efficient work. Toryo justified himself by saying, “I guess ‘pain in the ass’ people think of all kinds of ways to make things easier, so I'm always thinking of ways to improve my work...” (Toryo)
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