|
Hello. I am an Ignorant-Ignorant who excluded C language from my course registration in college. I've been learning a lot of things so far and I've made it to step 3, software design, of the production practice. |
This is the final chapter!
We are now going to design the circuit we designed in Step 2 in "software language" using Intel® Nios® II soft-core processor.
Will we be able to reproduce it?
Please also refer to Step 1 <Specification and Board Preparation> and Step 2 <Hardware Design>.
Table of Contents
- Incorporating Nios® II into your hardware design
- Design in C
- Putting the Nios® II boot program into the configuration data
- Things I didn't know
- Points that should have been done this way
- Summary
Incorporating Nios® II into your hardware design
To run a program written in C on an FPGA, incorporate the Nios® II soft-core processor (hereafter referred to as Nios® II).
For more information on Nios® II, please see this content.
We launched Platform Designer from Quartus® Prime and built the Nios II processor, the necessary modules, and peripherals such as PIOs.
| Hardware Design Image | Platform Designer (partial) |
Design in C
|
We need to design a C language to make the Nios® II reproduce exactly the same behavior that we designed in Verilog HDL (hardware language). So, Ignorant-Ignorant went through the materials he had used in his previous technical training courses. He found that the usleep() function could easily be used to create a clock. Using the while statement and the usleep() function, I created one second. In Verilog HDL, I used a clock as a base, but in C, there is a function that can stop the clock in increments of 1 second or 1 microsecond, which is very convenient! I made it so that the clock would continue to run until 23:59:59, and then return to 0:00:00 one second later. |
|
| Every 10,000 μs, set the flag to +1 When the time reaches 1 million μs (1s), go to the next loop. |
Putting the Nios® II boot program into the configuration data
Using the Run Configuration function of Quartus® Prime's Nios® II Software Build Tools for Eclipse (hereafter referred to as Nios® II SBT), the Ignorant-Ignorant thought he had completed the C program he had created by having Nios® II run it.
At this point, his senpai said, "Oh, yes, that's right.
Oh, that's right.
The Nios® II boot program is stored in the FPGA's on-chip memory,
And make sure that Nios® II is ready to run when the FPGA boots up.
After this, I realized that what I was doing was "just debugging.
In other words, after writing the hardware to the FPGA, I temporarily transferred the Nios® II program to the on-chip memory,
After the hardware was written to the FPGA, the Nios® II program was temporarily transferred to the on-chip memory to check the initial operation.
And then he left.
Oh, it's on the Web article!
Oh, a helping hand!
I immediately searched for the article he told me about and found the article "My First L-Tica with Nios II on Intel FPGA! Part 2 for reference.
As a result, I only need to supply power to the FPGA and Nios II will execute the program written by Ignorance-Ignorance, and I can operate 7-segment LEDs and dot-matrix LEDs on the expansion board.
Now I don't have to "download the software program after writing the hardware program.
(I agree that it would not be a product if I had to do that every time.)
And so, I finished Step 3 of the assignment.
Looking back...
Things I didn't know
How to integrate Nios® II into the hardware
The program that Nios® II executes is correct, but when debugging on the Nios® II SBT, there was "no response".
Even after making simple changes to the code, there is no change, and the "clueless clueless-kun" is petit panicky!
The reason for this was simply an operational error by Ignorant-Ignorant.
The reason was that the Nios® II system design created in Platform Designer "did not match" the system module names embedded in the Verikog HDL.
Normally, such a mismatch would result in an error when compiling Quartus® Prime.
In this case, since we were eager to "take the sample design and apply it from there!" because we were enthusiastic about the project,
This is because I was so eager to "take the sample design and apply it from there!
Moreover, the software project created in Nios® II SBT was created in .sopcinfo, which was not embedded in Verilog HDL, so the usage of Quartus® Prime was not clear, and I spent even more time to investigate the cause. We spent a lot of time to find the cause of the problem.
I should have "just looked at it for reference" instead of using the sample project as is.
|
Also, the consistency between the hardware design and software was resolved by using the System ID Peripheral Intel FPGA IP. (For an overview of System ID Peripheral Intel FPGA IP, please click here.)
I learned about it later from a senior colleague. I wish I had known about it earlier. |
Difference between Verilog HDL and C language processing
Contrary to Poki who wrote a blog about sequential processing and parallel processing, Ignorant -Ignorant is getting used to Verilog HDL and starting to understand the sense of parallel processing.
Compared to Verilog HDL's non-blocking assignment, which is parallel processing and can be written without worrying about the order, C language is sequential processing and the order of description is very important, such as when describing a loop in { } or an action outside { },
It took me a long time to get used to this rule.
For example
When designing a clock in hardware language,
As shown in the lower left figure, <minutes> counts up according to the value of <seconds>, and <hours> counts up according to the value of <minutes>, and <hours> counts up according to the value of <minutes>,
These actions (processes) are performed at the same time.
On the other hand, in the C language,
The C language, on the other hand, processes one by one, as shown in the figure below right.
|
Ignorant-Ignorant mumbling to himself. It is the C language that has by far the smallest amount of description, but I was quite confused at first. I was muttering to myself many times, "Oh, it's processed in order from the top...I see..." I think I was muttering to myself a lot in those days.
|
|
| Ignorant-Ignorant mumbling to himself |
Interval Timer Intel FPGA IP
|
Interval Timer Intel FPGA IP is a Node-based IP that is available in Platform Designer, The Interval Timer Intel FPGA IP is an IP that corresponds to the HAL API Driver for the Nios® II processor provided in Platform Designer. (I found out about this IP after the production training.)
This library seems to have a function called alt_ticks_per_second(). It seems to return the number of system clock ticks per second. It seems to return the number of system clock ticks per second, which could be applied to make a clock. |
Other functions such as alt_alarm_start() and alt_alarm_stop() can be used to create an alarm function for a clock without any complicated description.
You can even add an alarm function to a clock without any complicated description! (Maybe?)
These functions may be useful when creating clocks.
In the usleep() function used in the actual design,
The usleep() function is used in the actual design to stop all processing for a specified period of time while the clock is running, so that the clock can be run concurrently.
It was difficult for the clueless to write code for parallel processing,
to make the dot-matrix LEDs display complex messages.
However, with these functions
However, with these functions, it might have been possible to project a different animation onto the dot matrix LEDs while moving the clock.
I am left with a regret.
Not knowing is a loss.
Points that should have been done this way
In the software design (Step 3), we kept in mind the points that we have learned from Step 1 and Step 2 so far, so we did not make any terrible mistakes.
However, there were a few things that I realized that I should have done differently.
I should have grasped the entire workflow and clarified what needed to be done before proceeding.
I didn't do enough research to check the settings of various peripherals and to find out what functions could be used in the code.
I should have tried the contents (e.g., exercises) to get a sense of what to do before I started.
What? I think I said this line in Step 2...
I understood the importance of carefully setting IP parameters and creating the Nios® II development environment during Step 2, but I learned it all over again here at
in Step 3.
A problem occurred due to wiring in the air!
|
|
A few days before the production workshop presentation, A few days before the workshop, the 7-segment LEDs responded to the light touch of a hand on the pushbutton or its surrounding area! This was caused by wiring in the air. This was due to wiring in the air.
The wiring was incredibly unstable.
"Please keep me alive until the presentation!" I guess my prayers were answered, and we managed to make the presentation. |
If next year's new employees ask me, "Please show me how your expansion board is working," I will not be confident that the board is still alive at that time.
I am not sure if the board will still be alive at that time. I am sorry!
Summary
The in-house presentation of the training ended without incident, and Ignorant-Ignorant breathed a sigh of relief.
The things he learned through this training are now useful for his on-the-job training.
During the training, I had no idea what I was doing, but now I realize that there was no need to go through all that trouble!
Before the production training, I had a question for my seniors.
How can I multitask in my job?"
I replied, "There is actually no such thing as multitasking. There is no such thing as multitasking.
You focus on one thing at a time and use the time in between. It just looks that way thanks to detailed schedule management.
said a senior staff member.
You are right!
I suddenly remembered that,
I thought to myself, "This is just like dynamic lighting.
At the same time, I am ashamed of my past naivete in asking such a rough question just by the sound of the word "multitasking.
|
This concludes my story of the struggles of a new graduate in FY2022, Ignorant-Ignorant. I realize that in a few months, a junior employee will join our company.
I will continue to do my best so that I can become a dependable "ignoramus"! |
New Engineer's Blushing Blog Articles