How to set 30MHz as a Clock Constraint (It's that easy ... don't you think?)

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Introduction

Hello, my name is KURAMII.

I am currently studying timing analysis of Quartus® Prime in parallel with microcontroller exercises.
Timing analysis is to analyze whether a circuit works as expected even if signal delays are taken into account.
For an overview of timing analysis and its flow, please take a look at the article written by my senior, Masuo!

In this article, I would like to write about what I learned while studying timing constraints on clocks in timing analysis.

What are timing constraints?

How to give timing constraints in Quartus is described in detail in the article by Tophu, so I will skip it.

TimeQuest Timing Analyzer supports SDC.
SDC is in command format, so you have to remember which command to use for each constraint and what options (arguments) to use.
It's not easy.

As mentioned in Topu article, you can use Quartus to graphically place timing constraints.
For example, if you want to constrain the CLK port on your design to a frequency of 100 [ MHz ], you would enter the following as shown in Figure 1.

Figure 1.

Since frequency and period are inversely related, the value entered for Period is 10 [ ns ].
After completing the input, click the Insert button in Figure 1, and the SDC Editor will display the result as shown in Figure 2.

Figure 2.

It is convenient to give constraints easily!

While I was thinking about this, Mr. I, a senior member of the board, said to me.
"Well, how do you think we should constrain it to 30 [ MHz ]?"

The Period item must be entered in terms of period ( ns ), so first convert the frequency into a period.
Since frequency and period are inversely related,
1 / 30 * 10^6 = 33.3333... [ ns ]
.

If this is not divisible and becomes a circular decimal, we cannot give the exact 30 [ MHz ] constraint.
So what should we do?

After some research, we found that there are two ways. 1.

1. Use the options of the dedicated SDC command

By entering the following SDC command directly into the SDC Editor, it is possible to constrain based on frequency rather than period.

 create_clock -period 30MHz -name clk30MHz [get_ports clk]

2. Enter the Period entry to the third decimal place.

For example, if you want to set a constraint of 30 [MHz], you can enter "33.333" in the Period parameter, which means you have set a constraint of 30 [MHz].

The reason is that the SDC can be set to the third decimal place (the minimum is 1 ps), so if you enter the value to the third decimal place, it will be recognized as 30 [ MHz ].

Let's take a look at the two methods used to set the constraints!

Figure 3 shows the SDC file we will use this time. Figure 3 shows the SDC file we will use for this project, which has already been written except for the constraint on the main clock.

Figure 3.

First, let's look at the case where a dedicated command is used.
Enter the command directly on the second line of Figure 3.
In this case, we want to constrain the clock to 30 [ MHz ], so we enter -period 30MHz.
The name can be specified arbitrarily, so in this case we want to use the name CLK30MHz for simplicity, so we enter -name CLK30MHz.
This time, the target is the CLK port on the design, so enter [ get_ports CLK ]. (Figure 4 )

Figure 4.

After the input is complete, we do a full compilation and look at the Compilation Report and see that we are given a constraint of 30.0 [ MHz ] .(Figure 5 )

Figure 5.

Next, we would like to verify the "input to the third decimal place in the Period item".
Place the cursor on the second line of Figure 3, right-click, and select Insert Constraint → Create Clock.
Then, as shown in Figure 6, enter the data for each item and press the Insert button.

Figure 6.