Hello, this is Bee.
Last time we studied Power On Reset (POR).
How is the initialization time determined?
I searched for initialization in the handbook and found the following page
Configuration -> Configuration Process -> Initialization
(from "Configuration and Remote System Upgrades in Cyclone IV Devices")
" After the configuration data is accepted and CONF_DONE goes high, Cyclone IV devices require 3,192 clock cycles to initialize properly and enter user mode. "
As stated in the handbook, initialization takes 3192 clock cycles.
Then, if we know the clock frequency, we can calculate the initialization time.
So I made the following hypothesis.
"Since the clock (DCLK) is supplied by the FPGA in the AS mode configuration
I wonder if the clock during initialization is also supplied by the FPGA."
It seems my hypothesis was half correct.
There are two types of initialization clocks to choose from: internal clock (DCLK) and external clock.
Let's take a look at each case.
In AS mode, CLKUSR is supported only for the Cyclone® IV GX series.
" In Cyclone IV devices, the initialization clock source is either the internal oscillator or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization. "
Internal clock (using DCLK)
When using the internal clock, the frequency will vary depending on whether it is configured in Fast or Standard mode on the MSEL pin.
The following DCLK is described on Altera's website.
- In case of Fast Mode・・・ Max 40MHz, Min 30MHz
- In case of Standard Mode・・・Max 20MHz, Min 10MHz
Since my board is designed in Standard Mode, initialization time can be calculated as follows.
Initialization time = Number of clock rises * Clock period
- Worst Case: 3192 cycles * 100ns (10MHz) = 319.2μs
- Best Case: 3192 cycles * 50ns (20MHz) = 159.6μs
Now we know how long it takes to finish initialization.
Let's review again the time from when the power is turned on to when it enters the user mode (Worst Case).
Time to enter user mode = POR Time + configuration time + initialization time
= 200ms + 147.2ms + 319.2μs
= 347.5ms
External Clock
If the frequency of the external clock is not determined, the initialization time cannot be obtained.
Then, can we freely choose the frequency of the clock?
In extreme cases, can we put in 1 GHz? As expected, this is not the case.
The handbook stipulates that the external clock frequency is Max 40MHz.
The following is the text.
Configuration -> AS Configuration -> Single Device AS Configuration
(from "Configuration and Remote System Upgrades in Cyclone IV Devices")
So, how do you connect an external clock if you want to use it?
I checked the handbook and the Pin Connection Guidline!
Basically, the connections are the same as when using an internal clock.
According to the Pin Connection Guidline, if you use this pin, just connect it to the oscillator.
If not used, it must be connected to GND.
Also, it seems that Quartus II also needs to be set up. I actually tried to set it up on Quartus II.
You can set whether the CLKUSR pin is used or not by the following two steps.
Check CLKUSR at Assignment -> Device -> Device & Pin Options -> General
Select the clock source at Asignment -> Device -> Device & Pin Options -> Configuration -> Active serial clock source (* This option is supported only for Cyclone IV GX. )
After compiling with the above settings, the information is indeed reported.
The following is how to check it.
Compilation -> Fitter -> I/O Rules Section -> Device Option
When should I turn on the external clock and when should I stop it?
Looking at the timing charts for the PS and FPP mode configurations, CLKUSR is enabled after 4 DCLK cycles.
Furthermore, if we want to stop the external clock after initialization, it would be better to stop it by looking at the INIT_DONE pin!
The following figure shows how the configuration signal works.
Now we know how long it takes to get into user mode after the fire is turned on!
But here, I have a new question.
POR is the time to reset the FPGA.
Initialize is the time to assign zero (initial value) to a register in the FPGA.
I don't understand the difference between these two points...
Reset and initialize seem to be the same.
Next time I will study the difference between initialize and POR.
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