Introduction
Hello, my name is Kuramii!
As I have been practicing production using FPGAs, a new question has arisen.
The question is ’Will my design exceed the logic capacity of the FPGA I plan to use?’
After much research, I came to the conclusion that you cannot know how much logic your design has until you register your design with Quartus® Prime and Compile it.
Therefore, you don't know if your design will exceed the logic capacity of the FPGA you plan to use.
But!
There are several ways to estimate in advance, and I have considered various patterns.
1. when you improve a previously created design
1. when improving a previously created design
First, estimate how many new functions you wish to add. For example, if you want to add an 8-bit counter circuit that continuously counts up in response to the CLK signal and an LED that lights up when the switch is pressed, you can imagine the following diagram. (Figure 1)
Figure 1: Design Example
Imagine Figure 1 and approximate the number of logics. Then, add the number of logics for the new function to the total number of logics from the previous design to get the approximate number of logics after the improvement.
2. When creating a new design
Since there is no way to estimate this number, you will need to Compile the design with Quartus Prime.
In that case, a full compilation will give you the total logic count after place and route.
If you want to estimate the number of logics before place and route, check the number of logics after logic synthesis.
Let's look at the Compilation Report after performing Start Analysis & Synthesis in Quartus® Prime. (Figure 2)
Figure 2. Compilation Report After Place and Route
Figure 2 shows that there are 1727 total logic elements before Place and Route.
Next, let's look at the Compilation Report after Start Compilation. (Figure 3)
Figure 3. Compilation Report After Place and Route
Figure 3 shows that the Total logic elements after Place and Route is 1657.
The Compilation Report after Place and Route shows what percentage of the FPGA's logic capacity is used by this design.
This raises a further question.
Why is the number of logic elements before and after Place and Route different?
The number of logics before Place and Route is the estimated number of logics derived from the result of logic synthesis.
In contrast, after full compilation, the result is obtained after all place and route routing is completed, so the actual number of logics used can be confirmed.
As you can see, the number of logics after place-and-route changes due to optimizations such as register packing. In this case, the number of logics after full compilation is smaller, but note that this does not necessarily mean that the number of logics will be reduced.
3. When Nios II is used
I am also working on production practice using Nios II, but how much is the number of logic when using Nios II?
Nios II is ALTERA's soft core CPU.
This "soft" does not mean software. It is "soft" in the sense that the logic of the FPGA is used to configure the CPU.
The circuitry of the CPU is not included in the FPGA from the beginning. When Nios II is implemented in FPGA, the logic area of FPGA is used.
Figure 4. Diagram of Nios II implementation
Since Nios II is a CPU, it does not function by itself.
Therefore, other necessary Peripheral IP is incorporated, and the FPGA logic is used for the number of logic elements in that IP.
Figure 5. Nios II IP Peripheral
In addition, a bus is required to connect Nios II and the IP, so the bus capacity is also used.
Therefore, the total logic capacity used to implement Nios II in an FPGA is the capacity of Nios II itself + the capacity of the IP to be used + the capacity of the bus.
Table 1 shows the estimated logic capacity for Nios II in the Economy/Fast case.
Table 1 . Estimated Logic Consumption for Nios II Implementation
4. using an SoC device
In this case, the Hard Processor System (HPS) part, which includes the CPU (ARM) and peripherals, is already embedded in the SoC device (Figure 6).
Figure 6. Diagram of the HPS
The HPS part is a fixed circuit and does not affect FPGA resources.
In other words, the number of logic elements in an SoC device is determined only by the circuits implemented in the FPGA.
In Closing
Now you know what kind of FPGA with what kind of logic capacity you should choose for your design.
Please look for the next article in this series!
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