Introduction
This is "Poki".
In the production training, I created a board and circuits that would allow me to use FPGAs to perform the operations I wanted.
When the board was completed, one of my seniors said to me, "Configuration has been completed successfully,
One of my seniors asked me, "Why don't you check with an oscilloscope to see if the configuration has been completed normally and if it has entered the user mode?
"Why don't you check with an oscilloscope to see if the configuration has been completed successfully and you have entered the user mode? I was told to check with an oscilloscope to see if the configuration had been completed successfully and the board had entered user mode.
This time, I used Intel's configuration ROM "EPCS16".
When using EPCS16, it is in Active Serial (AS ) configuration mode.
Indeed, AS configuration is not the same as JTAG configuration.
Because the Quartus® II on the PC does not display success or failure,
The only way to know if the configuration was successful is to see if the user circuit is working or not.
Please refer to the article "What is Configuration Mode?
So, I decided to look at the signals that can confirm that the configuration has been successfully completed.
Which pins should we look at?
There are many pins related to configuration.
Figure 1 shows the timing chart during AS configuration.
Figure 1 : Active Serial Configuration Timing Chart
(Source: Serial Configuration (EPCS) Devices Datasheet)
There are two types of FPGA pins that indicate the completion of configuration.
- CONF_DONE : Signal that goes Low -> High (external pull-up) when all configuration data has been received and completed without error.
- INIT_DONE : Signal that goes High (external pull-up) when all configuration data has been received and initialization is completed and the device enters user mode.
This time, we decided to take a look at the INIT_DONE pin, which has not been used before.
The behavior of the INIT_DONE pin during configuration is as follows.
"High" at power-on → "Low" during configuration → "High" at the end of initialization
Huh? Where is it?
This INIT_DONE pin is treated as an Option, so first enable this pin.
To enable the INIT_DONE pin, click on the Quartus II menu
Assignments → Device... → Device & Pin Options... → General in the Category
Check the Enable INIT_DONE output checkbox.
After enabling the INIT_DONE pin, I tried to place the INIT_DONE pin in Pin Planner, but..,
What? There is no INIT_DONE pin!
In addition, nCS0, DCLK, ASD0, and DATA0 in Figure 1 are also missing.
So I decided to ask for help from my senpai.
Originally determined signals
Poki: "Senior, the configuration pins do not appear on the Pin Planner,
How should I place the pins?"
Senior: "nCS0 , DCLK, ASD0, DATA0, and INIT_DONE are signals that originally had to be pinned to a specific pin on the device, so you don't have to do any pin placement.”
Poki "Does that mean it is not shown on Pin Planner?"
Senior "No, it will be shown by doing Back-Annotate Assignments."
Back-Annotate Assignments
Back-Annotate Assignments is a way to reflect information such as pin assignments automatically set by Intel® Quartus® Prime at compile time in your own settings.
To do this, after compiling, go to the Quartus II menu Assignments → Back-Annotate Assignments....
After compiling, go to the Quartus II menu Assignments → Back-Annotate Assignments..., make sure that Pin & Device assignments is checked, and press OK.
This will take effect.
If you look at the Pin Planner, you will see...,
The information of the dedicated pins that have been assigned appears!
I feel at ease now!
But then a senior colleague gave me some advice.
Cautions for Back-Annotate Assignments and Pin Information
My senior said, "But when you execute Back-Annotate Assignments, it automatically sets the user I/O pins that have not been assigned to any pin to any pin, so be sure to set the pins with fixed pin assignments first."
The user I/O pins within your own design must be pinned to match the board you have created.
If you do not do this pin placement yourself, Intel® Quartus® Prime will place the pins at compile time, completely unrelated to the board information.
Senior "Also, information on the originally assigned dedicated pins can be found in the device's pinout file, so you should look at that before placing the user I/O pins."
You can download the pinout file from Intel's website, which contains device pin information.
Pinout File for Intel® FPGA Devices".
If you place a user I/O pin on a dedicated pin that has a fixed placement, the following error will occur.
(I deleted the pinout information for PIN_98, which is an INIT_DONE pin, and forced other pins to be placed.)
I can avoid this Error by avoiding such dedicated pins in the board design stage.
Check the waveform with an oscilloscope
Now that we know which pin is assigned to the INIT_DONE pin, we put in a pull-up resistor and looked at the waveform during AS configuration.
The waveforms are "High"→"Low" → "High", which is the behavior of the INIT_DONE pin during configuration,
This indicates that the AS configuration has succeeded and the device has shifted to user mode.
We now know that AS configuration has been completed.
Today's POINT
- Check the dedicated pins in the pinout file before placing user pins
- Configuration-related dedicated pins are displayed on the Pin Planner by Back-Annotate Assignments after compilation.
- Back-Annotate Assignments are done after placing user pins because Quartus II automatically places pins that are not placed at compile time.
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