Hello. I'm Totto, and I regret every day that I did not check the I/O functions in the early stages of board fabrication.
At the end of the last issue, I found the following table and a question arose.
It is,
･The sign of "IOH" is Negative
･The sign of "IOL" is Positive.
Why is "IOH" negative? Why "IOL" is positive?
My senior taught me that from the FPGA side, there is a difference between current coming in and current going out.
I wondered what he meant by current coming in when it is output current.
This is what was going through my mind.
This question was easy to answer when I considered the CMOS circuit in the FPGA.
The figure below shows a CMOS circuit for a portion of the output buffer of an IOE.
As shown in Figure 1, the current did not flow in the same direction when the voltage was high and when the voltage was low.
Totto felt that electricity is a very deep subject and that he was one step closer to safely handling FPGAs.
Totto's IOE adventure will continue in the next article...
Summary of this time
When the output voltage is high, current flows from the FPGA side ( out of the FPGA. )
↓
The sign of "IOH" is Negative
When the output voltage is low, current flows into the FPGA side ( coming into the FPGA. )
↓
The sign of "IO L" is Positive sign of "IO L
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