Introduction
Hello, my name is KURAMII.
This time, I would like to deviate from the C language struggle a little and introduce the difference in usage between RTL Viewer and Technology Map Viewer in Quartus® Prime.
RTL Viewer
First, let me introduce the RTL Viewer function.
This function is used after Analysis & Elaboration.
Figure 1 shows an example of an VHDL circuit created, and Figure 2 shows the circuit displayed in RTL Viewer.
Figure 1 HDL Circuit
Figure 2: An example of RTL Viewer
The green box represents the hierarchy, and clicking the + symbol allows you to view the inside of the logic block.
Figure 3 shows the view after clicking the + mark for simple_counter in Figure 2.
Figure 3. contents of block (simple_counter)
The components of RTL are I/O pins, registers, gates (AND, OR, etc.), operators (adders, multipliers, etc.), etc. Thus, using RTL Viewer, you can check your design schematically.
It can also be used for debugging, since it displays the design with optimizations such as connection checks and unconnected ports. I found RTL Viewer to be very useful in my production practice, as it allowed me to see unconnected I/Os that I thought were connected.
Technology Map Viewer
Next, I would like to introduce the Technology Map Viewer function. By launching this viewer, you can graphically check the circuit after logic synthesis and placement and routing (Figures 4 and 5). (Figures 4 and 5) Technology Map Viewer has Post-Mapping and Post-Fitting.
Post-Mapping
Post-Mapping】 Allows you to check circuits after logic synthesis by putting them into primitives such as logic elements, memory blocks, I/O elements, and so on.
Post-Fitting
Post-Fitting] Circuit after placement and routing, reflecting the optimization performed at the time of placement and routing.
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Figure 4, Example of Technology Map Viewer (Post-Mapping) |
Figure 5, Example of Technology Map Viewer (Post-Fitting) |
Figure 6 shows a view of the inside of a logic block by clicking the + symbol in the simple_counter hierarchy.
The blue boxes represent logic elements and the green boxes represent registers.
You can see that what was shown as Add (adder) in RTL Viewer was actually configured as shown in Figure 6.
Figure 6: Post-Fitting: Composition of simple_counter
The components of the Technology Map Viewer include I/O pins, logic cells (LCells), and memory blocks.
Using the Technology Map Viewer, you can see how your design was realized by Quartus® using the logic cells inside the FPGA. If you want to graphically check the final result after both logic synthesis and placement and routing are finished, it is convenient to use Post Fitting's Technology Map Viewer.
＜Things that are useful to know＞
In both RTL Viewer and Technology Map Viewer, left-clicking the cursor on a path highlights the path (Figure 7).
Figure 7 Highlighting a path
2. using the Filter, you can pinpoint the selected area.
For example, to pinpoint simple_counter, right-click on simple_counter and select Filter. (Figure 8)
Figure 8.
In this case, we have selected Sources, one of the Filter functions.
This allows us to see what paths are connected to the selected input.
Conclusion
The difference in usage between RTL Viewer and Technology Map Viewer is as follows
◎RTL Viewer
When you want to see the design diagrammatically.
◎Technology Map Viewer
When you want to see schematically the design mapped to the logic cells inside the FPGA.
The above two functions are very useful to check and debug your design smoothly!
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