During the clock fabrication practice, we were told that we should at least do AS-mode configuration, not just JTAG-only configuration mode.
Certainly, JTAG configuration is the best for production practice, where the FPGA data can be rewritten each time because there is a high possibility of making logic mistakes, but JTAG configuration is unlikely to be optimal for the customer's products.
However, JTAG configuration is unlikely to be optimal for the customer's products. Writing data to products installed in various locations via JTAG would require engineers to be attached to each product.
Too much labor cost.
So, we looked into the configuration process.
The configuration process can be divided into three categories.
Altera download cables are used.
Serial configuration memory
General-purpose parallel flash memory.
I will try to list the advantages and disadvantages of each of these configurations for the customer.
The configuration modes are as follows
Active Serial (using serial configuration memory)
Active Parallel (external control circuit or program + general-purpose parallel flash memory)
JTAG (using Altera download cable)
Passive Parallel (using general-purpose parallel flash memory)
Fast Passive Parallel (using external control circuit or program + general-purpose parallel flash memory)
Serial and Parallel refer to whether the configuration data is serial or parallel data.
Serial: the configuration data is serial
Parallel: the configuration data is parallel
It can be inferred that the configuration time is faster with parallel data than with serial data.
Active and Passive seem to indicate from which side the clock is driven.
Active: Cyclone® IV device outputs clock for configuration
Passive: Cyclone IV device receives configuration clock
The recommendation for Active Serial (AS) mode makes sense.
For those of us who have difficulty creating a control circuit or program for configuration, the Active Serial mode proved to be the best as long as we could connect the device as described in the handbook.
The question is, how does the device recognize multiple configuration modes?
The Cyclone IV handbook, Section III -> Configuration -> Configuration Scheme, described the following
The configuration mode is selected by the MSEL pin of the FPGA.
In the R&D phase, configuration in JTAG mode is recommended, but for mass production, the suggested mode depends on the product specifications.
For mass production, the suggested mode depends on the product specifications: AS mode using serial configuration memory for easy configuration, or a combination of CPU and general-purpose flash memory already planned for other functions if the number of components cannot be increased.
If the configuration fails, it becomes just a board. I recognized that configuration is very important.
Now we have decided on the configuration mode. Next, we need to select the configuration memory for Altera.
In the next article, we will introduce the selection of configuration ROM.
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