Hello, my name is Toryo.
In this second installment of the "Newcomers Poke Their Heads Into New Territory" series, I would like to introduce some useful information on tool specifications based on the "uneasy relationship" between complex processing technology and FPGAs.
One day, a customer called with a question about Quartus® II.
The newcomer, thinking to himself, "Tool, Quartus II...", replied, "Yes, it's a question about Quartus II. I'm here to help you. I asked him what he wanted to know.
What criteria does Quartus II use to decide whether to use the DSP block or the internal logic during logic synthesis?"
Dooooooooooooooooooooooooo! sounded in my head.
Quartus II's decision criteria? What should I do...?
After telling him that I would call him back and hanging up the phone, I first looked into the "mysterious relationship between DSP and FPGA.
DSP stands for Digital Signal Processor or Digital Signal Processing, but the DSP Block in Altera's FPGA is a digital signal processing block that performs arithmetic operations on digital signals. Digital Signal Processing. In this column, we will use the term DSP to refer to digital signal processing.
DSP is mainly used in various applications such as video surveillance systems, broadcasting equipment, wireless base stations, medical image processing, and radar.
Altera FPGAs provide DSP blocks containing multipliers and adders as hard IP to enable fast and efficient arithmetic operations.
For more information on DSP solutions with Altera FPGAs, see "Technology" > "DSP" at the top of the Altera home page.
You will find new features in the latest devices, IP, reference designs, documentation, and more.
To implement DSP in an Altera FPGA,
1. use DSP blocks
2.Using internal logic
There are two ways to implement DSP in Altera FPGAs
Incidentally, the names of the DSP block and internal logic are "slightly" different depending on the device family.
*For the latest Cyclone V, however, they are called DSP blocks/ALMs, as in Arria V and Stratix V.
And there are three ways to do a design that includes DSP
1. assemble your design using IP provided by Altera
2. create your own HDL description-based design
3. create a computational model using Altera's DSP Builder library in the MATLAB® / Simulink® environment provided by MathWorks and convert it to HDL.
In the case of 3, it is possible to control which DSP block or internal logic is used on DSP Builder.
However, when we asked the customer about this case, he said that he used the pattern 2, and as a result of performing Analysis & Synthesis on the multiplier written in HDL, he used the internal logic instead of using the DSP block.
Although the internal logic can be saved by using a DSP block in the arithmetic processing part, unexpectedly, this time we have wasted a lot of resources.
What criteria does Quartus II use to make such decisions?
I asked my senior.
Senior "Well, that's a very good question, but very difficult to answer.”
Toryo "What do you mean?”
Senior "There are various factors that determine whether it is a DSP block or internal logic, so it is hard to say in one word.”
ToryoToryo "Really?”
Senior "I wondered the same thing before and tried various things, but it seems that even if the HDL description is the same, the synthesis result varies depending on the constraint conditions, target device, structure of the peripheral circuits, and resource usage.”
For example, if I change the target device and do Analysis & Synthesis of this self-made multiplier..."
Senior "You see. The design is the same, but one uses the resources of the DSP block and the other does not.
Toryo "Wow. So it's really an "iffy relationship.
Senior "Quartus II selects resources to optimize timing and area during the synthesis and fitting phases.
Toryo "Seriously...I'm at a loss. I can't answer to the customer..."
Senior "But there is a way to "prioritize" which to use!
Toryo "Oh! There is such a setting?
Senior "Actually, there are two settings..."
Toryo "Yes, two! Two!
Senior "There are four ways to apply the settings. 1.
1. settings to be applied to the entire circuit in a .tcl or .qsf file.
2. settings applied to individual instances in .tcl or .qsf files.
3. settings to be applied to the entire circuit, based on the Quartus II GUI.
4. settings to be applied to individual instances, based on the Quartus II GUI.
Senior "First, for the first method, when you open a .qsf or .tcl file, the default setting is "AUTO", so you need to change the relevant part as follows
set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS" "2.
Senior: "The second method is to put the following in the same file
set_instance_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS" -to *****
Toryo: "Oh, well."
Senior "At the end of this description, following "-to", write the name of the instance to be set in "*****"."
Toryo "I see. Then, how can I set it up in Quartus II like 3 and 4?"
Senior "I will explain now."
3. setting up the entire circuit using Quartus II
Senior "Go to Assignments > Settings > Analysis & Synthesis Settings > More Settings > DSP Block Balancing and make your selection from the pull-down menu. "
4. setting individually using Quartus II
Senior "In the Assignments > Assignment Editor, pull down the Assignment Name and select "DSP Block Balancing" and in the Value field select the value you want to set."
Toryo "Oh, I see! It's easy to set up in Quartus II, isn't it!"
Senior "Yes, yes! Using these settings, you can configure it to use DSP blocks, and then compile it..."
Toryo "Oh! It is reflected properly."
Senior "That's great!"
Toryo "I'm glad!"
Senior "Well, you should learn more about FPGA technology and support me this time."
Toryo "Yes, I will do my best! I will do my best."
In this way, the chieftain was able to answer the somewhat complicated question.
The chieftain promised himself that he would continue to pursue technology further and provide high quality support instead of "vague" answers to difficult questions.
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