Hello, my name is Taro. This time I will write about SER.
What is SER?
SER stands for Soft Error Rate and refers to the percentage of LSI malfunctions caused by radiation.
SER is sometimes used as a synonym for Hard Error, which is caused by physical destruction of transistors, etc.
It is important to note that a semiconductor chip in which Soft Error has occurred is not physically destroyed.
In other words, since it has not been physically destroyed, it will return to normal operation by rewriting data or turning the power back on.
For example, in SRAM, data is held in memory cells by storing an electric charge, but a collision with ionizing radiation, which discharges the charge, disturbs the value, resulting in a memory error.
How to Evaluate SER
The degree of device EMI (see "PLL Applications (Reduce EMI by Spread Spectrum!)") can be investigated by neutron beam irradiation or by placing a radioisotope in the vicinity of the device. ), neutron beam irradiation, and placement of radioisotopes in the vicinity of the device, all of which are accelerated tests.
Accelerated testing refers to testing in which the measurement time is much shorter than the actual use time, not the actual use time.
I mistakenly thought that accelerated testing was a test in which the system is run at a clock frequency above the specified frequency.
Running a device at a higher clock frequency than specified is called overclocking.
As a technical support person, I do not recommend this type of usage.
If a problem occurs when a device is used above the recommended operating range, it will not be covered by our support.
Please be sure to use the device within the recommended operating range.
Semiconductor Chips, Going to the Mountain
The above acceleration test is not a strict reproduction of the actual operating environment and tends to be severe.
When estimating the effects of soft errors, semiconductor chips are sometimes tested by placing them in high mountain areas.
In Europe, there is a facility in the French Alps called ASTEP (Altitude SEE Test European Platform) that measures radiation from cosmic rays.
ASTEP is located at an altitude of 2,552 m, which is about six times higher in neutron radiation than at sea level. The ASTEP is located at an altitude of 2,552 m.
I had an image that semiconductor devices are tested indoors, so I felt this was very unexpected.
About Altera's SER countermeasures
Altera FPGAs have a built-in error detection circuit (CRC: Cyclic Redundancy Check circuit).
(For details on CRC support, please refer to the handbook for each device family.)
The CRC circuit inside the FPGA can be easily enabled by using the Quartus® II option of Altera's Place and Route Tool.
See here for more details.
In addition, the latest SoC FPGAs also have enhanced Soft Error countermeasures.
For more information on SoC FPGAs, please click here.
There really are a lot of things to consider in manufacturing, aren't there?
That's all for now, Taro.
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