Let's try using the FPGA system debug tool "System Console

Hello, my name is Intel F. Hanako.

My name is Intel F. Hanako and I am a technical support engineer for Intel® FPGA products at Macnica.

The System Console is a debug tool in Quartus® Prime that allows you to debug via JTAG while running your design on the FPGA.
It allows register access to peripherals connected to the System Console via JTAG, as well as checking the JTAG master clock.
Simple register accesses can be debugged on the System Console even if the Nios® II processor is not implemented.

In this issue, we will introduce the System Console using a simple sample.

Target Environment

Quartus Prime

Pro Edition / Standard Edition / Lite Edition

Target devices

All devices supported by each edition of Quartus Prime

Communication Cable

Intel FPGA Download Cable II (formerly USB-Blaster II)

On-Board Intel FPGA Download Cable II

Intel FPGA Download Cable (formerly known as USB-Blaster)

On-Board Intel FPGA Download Cable

Usage Requirements

To use the System Console, your project design must

To use the System Console, one of the following peripherals must be included in the project design

　・　JTAG to Avalon Master Bridge (JTAG Master)
　・　Nios II Processor (with JTAG Debug Module)
　・　USB Debug Master
　・　Avalon-ST (Streaming) JTAG Interface
　・　JTAG UART
　・　Ethernet Components

Sample Design

The sample design used here consists of the following components.

This time, the System Console is used to check the status of the clock and reset signals,

PIO of DIP switches, PIO of LEDs, and on-chip RAM.

Sample Design Configuration

In this section, we will introduce the operation using the GUI of Quartus Prime Standard Edition.

Debugging Flow of System Console

The workflow for using the System Console is as follows:

　1. Add and generate IP cores in the Platform Designer system

　2. Compile your design

　3. Connect the board and configure the FPGA

　4. Launch System Console

　5. Specify service path and identify services

　6. Start the service

　7. Perform debugging operation

　8. Terminate the service

1. Add and generate IP cores for the Platform Designer system

The IP required to use the System Console is built into the Platform Designer system.

The components used in this sample design are as follows

　・　Nios II Processor (with JTAG Debug module)
　・　JTAG to Avalon Master Bridge
　・　On-Chip Memory Intel FPGA IP
　・　PIO Intel FPGA IP (2)

Note :
If you only need simple register access, you can debug with Nios II alone, but this time, JTAG to Avalon Master Bridge is also connected to use JTAG Debug service (command).

After registering each component in Platform Designer, connect them in the System Contents tab.
Connect the Avalon Memory Mapped Master (Avalon MM Master) to the Avalon Memory Mapped Slave (Avalon MM Slave) of the component you wish to operate.

Note:
In this example design, the Master service is performed by the Avalon MM Master on the Nios II, and the JTAG Debug service is performed by the Avalon MM Master on the JTAG to Avalon Master Bridge.

The figure below shows the connections in this sample design.

After completion, save the Platform Designer system and run Generate HDL.

2. Compile the Design

Incorporate the Platform Designer system into the design and register it with the project.

Then, compile the design.

3. Connect the board and configure the FPGA

1) Connect the board to the download cable and apply power to the board.

2) Start Quartus Prime Programmer and configure various settings such as Hardware Setup, selection of sof file to be downloaded, etc.

3) Click "Start" button and configure the FPGA.

4) Close the Programmer.

Note that the FPGA configuration (.sof file download) can also be executed from the System Console using the device command device_download_sof instead of performing the configuration here.

For details, see "4. Launch System Console”

4. Start the System Console

1) Start the System Console.

　 There are three ways to start the System Console, so choose the method that best suits your development situation.

　　A) Tools menu of Quartus Prime > System Debugging Tools > System Console

　　B) Tools menu of Platform Designer > System Console

　　C) Start Nios II Command Shell and enter system-console.exe command.

2) Click System Console's File menu > Load Design and select the .sof that you have downloaded (or will download).

<If you have already downloaded the .sof, go to the next step. >

3) For the FPGA you are connecting to under the devices folder in the System Explorer pane,

　 Right click > Program device > "sof file" for the FPGA you want to connect to under the devices folder in the System Explorer pane.

Alternatively, you can configure the FPGA by entering the following command in the Tcl Console pane.

 % get_service_paths device
 % set dpath [lindex [get_service_paths device] 0]
 % device_download_sof $dpath "path of sof file" 5.

5. Specify the service path and identify the service.

1) In the Tcl Console pane, use the get_service_paths command to specify the path and identify the service.

　 Note that a list of service types can be found with the get_service_types command.

For example, in this sample design, the master service is used to "access PIO of DIP switches, PIO of LEDs, and on-chip RAM.

Enter the following to obtain the path to the master service.

 % get_service_paths master

In the sample design, two Avalon MM Masters are shown.

In addition to the log of the above command, you can also check the log under the devices folder > FPGA model number > (link) folder > JTAG folder in the System Explorer pane.

2) The sample design reads and writes each memory-mapped slave via the Nios II Avalon MM Master, so create a variable that points to the Nios II (Avalon MM Master) component by entering the following.

　Where mpath is the variable. lindex is 1.

 % set mpath [lindex [get_service_paths master] 1]

6. start the service

Start a connection to the specified service with the claim_service command.

 % claim_service master $mpath ""

To facilitate debugging, create a variable for the started service with the following command.

 % set master_path [claim_service master $mpath ""

Note : When using the above command, claim_service master $mpath "" is not necessary because it is used at the same time.

7. Perform debugging operation.

Verify the connected device using the $mpath "" command.

The following are some examples of commands in this sample.

To verify the clock and reset signals / To issue a reset signal

Use the jtag_debug service.

In the sample design, the service is accessed via the Avalon MM Master of the JTAG to Avalon Master Bridge, as shown below.

　 * jdpath is a variable. lindex is 0.

 % set jdpath [lindex [get_service_paths jtag_debug] 0]
 % jtag_debug_sample_clock $jdpath
 % jtag_debug_sample_reset $jdpath
 % jtag_debug_reset_system $jdpath

jtag_debug_sample_clock : returns the value of the clock signal (multiple sampling is required to confirm toggling)

jtag_debug_sample_reset : Returns the value of the reset signal.

jtag_debug_reset_system : issues a reset to all components connected to the Avalon to JTAG Master component.

To check the ON/OFF status of the DIP switch

 % master_read_8 $master_path 0x10020 1

master_read_8 : Read the value of the specified address.

　　0x10020 : Address of PIO for DIP switch

　　1 : Size to be read

Controls the turning on/off of LEDs.

 % master_write_8 $master_path 0x10000 0x1F
 master_write_8 $master_path 0x10000 0x0

master_write_8 : Write to the specified address

　　0x10000 : Address of PIO for LED

　　0x1F, 0X0 : Value to be written

Read/write on-chip RAM

 Read/write on-chip RAM % master_read_32 $master_path 0x8000 32

master_read_32 : Read the value of the specified address

　　0x80000 : Address of on-chip RAM

　　32 : size to be read

 % master_write_32 $master_path 0x8000 {0 1 2 3 4 5 6 7 8 9 10}

master_wrote_32 : Write to the value at the specified address

　　0x80000 : Address of on-chip RAM

　　{0 1 2 3 4 5 6 7 8 9 10} : Value to be written

For other commands and services, please refer to the following documents

Quartus Prime

Reference Documents

Standard Edition

Lite Edition

Analyzing and Debugging Designs with System Console

From "Intel Quartus Prime Standard Edition User Guide: Debug Tools

Pro Edition

Analyzing and Debugging Designs with System Console

From Intel Quartus Prime Pro Edition User Guide: Debug Tools

8. close_service

The close_service command closes the connection to the service started in operation 6.

 % close_service master $master_path

[Advanced] Execution via Toolkit API

By using the Toolkit API service, it is possible to visualize debugging data and display it in graphical widgets such as buttons, text boxes, bar graphs, and dialogs. Toolkit API services can be used to visualize debugging data and display it in graphical widgets such as buttons, text boxes, bar graphs and dials.

In the next issue, we will introduce the Toolkit API.

Toolkit image