Hello, my name is Masuo.
Starting this week, I will be serializing a new project, "Timing Analysis Series - 6 parts"
The most difficult part of the newcomer training was the timing analysis lecture. In this column, I would like to summarize the lecture materials and notes on timing analysis and introduce some of the points that I stumbled upon.
Fmax ( maximum operating frequency )
Timing analysis verifies whether an FPGA operates correctly at a certain clock frequency.
Fmax is the maximum frequency at which the FPGA can operate and is defined by Equation 1. You are calculating how much data can reach the receive register from the transmit register in one clock cycle!
Figure 1. Definition of Fmax
TDATA Delay : Data delay time. It depends on the circuit design.
TCLK2 - TCLK1 : Clock skew. Depends on wiring.
μTSU : Setup time. The time that data must be fixed and held in advance for the input clock edge of the register. Device-specific value.
μTCO : Clock to Output. Time required for data to be output in response to the input clock edge of the register. Device-specific value.
From Equation 1, we see that Fmax is dependent on "circuit design" and "clock skew.
Altera FPGA devices contain dedicated routing areas (Global Clock, Regional Clock, etc.) that are tuned to minimize clock skew. Since clock skew = 0 (i.e., Tclk2 = Tclk1 ) when clock signals are routed to the Global Clock, Equation 2 can be obtained by fitting the values to Equation 1.
From Equation 2, Fmax depends on the "circuit design.
The user is expected to design for the expected value of Fmax.
Setup Time and Hold Time
To acquire data correctly, data must be stable before and after the clock edge (Figure 2).
Setup time (Tsu): Time during which data (DATA) must be finalized before the clock edge.
Hold Time (Th): Time after the clock edge that data (DATA) must be held.
Figure 2. Setup Time and Hold Time
Timing analysis analyzes the paths between all registers to ensure that the setup and hold times are met.
If the timing of the data and clock edges do not match, a setup time/hold time violation has occurred.
Suddenly, here is a quiz!
With respect to the leftmost clock edge in Figure 3, which is earlier/slower in time, dataA or dataB?
Figure 3. flow of DATA
The answer is: dataA => slow dataB => fast.
Masuo was under the illusion that "dataA is ahead of dataB in the direction of data flow, so dataA is ahead of dataB in time" (← stumbling point).
However, when expressing the movement of a logic circuit, the time axis is represented from left to right. In other words, in relation to the clock edge
The left side is faster on the time axis
The right side is slow on the time axis.
The left side of the time axis is faster than the right side of the time axis.
I realized that looking at the effective range of data relative to the clock edge is a very important point in understanding timing analysis!
The conclusion is that when data arrives late relative to the clock edge, a setup time violation has occurred, and when data arrives early, a hold time violation has occurred. (Figure 4)
Figure 4. Setup time violation and hold time violation
| Conclusion |
| ･The Fmax parameter is greatly affected by the "circuit design" (Equation 2). ･Setup time violation occurs when data arrival is slow relative to clock edges. ･When data arrival is early relative to the clock edge, a hold time violation occurs. |
In the next issue, we will introduce the SDC file, which is always necessary for timing analysis!
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