Introduction
Hello. My name is Totto.
My senior said to me, “FPGAs don't break that easily." But I'm always scared of the FPGA on the board that I made, and I'm always scared when I turn on the power.
This time, I tried to find out when an Open Drain is used and why a high impedance state is necessary.
Me : "When is Open Drain used?"
Senior: "Do you know how to connect digital ICs with different voltage levels? Me : ""
Me: "・・・・・・・・・・・"
After damaging the FPGA, I realized the danger of not being able to connect directly to the FPGA, and this is what I saw in my mind.
As a new engineer, I thought why don't I just use the Open Drain of the FPGA output buffer and pull it up with 5V?
To connect digital ICs of different voltage levels: ・・・・
There are two types of FPGA signals: single-ended and differential.
Single-ended signals are recognized by the FPGA as high if they are higher than a certain voltage value specified in the standard, and as low if they are lower.
The input threshold is satisfied, so the connection is OK.
Connection is NG because the input threshold is not met.
Here, the Open Drain of the FPGA output buffer can be utilized.
Using the Open Drain on the FPGA output buffer...
I thought that by using the Open Drain on the FPGA output side to put the output in a high impedance state and pull it up, the input threshold could be satisfied regardless of the output voltage.
But...
To be continued in the next issue!
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