Hello, my name is Intel F. Hanako.
My name is Intel F. Hanako and I am a technical support person for Intel® FPGA products at Macnica.
Do you know that there is a debugging method other than oscilloscope or logiana when debugging Intel FPGAs on real machines?
It is Signal Tap!
SignalTap® II has been renamed Signal Tap since Quartus Prime 17.1.
Signal Tap Logic Analyzer Configuration and Block Diagram
The Signal Tap logic analyzer is officially called the Signal Tap logic analyzer.
Simply put, it is a Quartus® Prime logic analyzer function that monitors the internal signals of user circuits implemented in FPGAs.
Its features are
- Signal Tap IP is implemented in a free area of logic elements (LEs) and memory inside the FPGA
- Display of observed data on the Quartus® Prime screen
- Communication between the board and Quartus® Prime is via a download cable such as the Intel® FPGA Download Cable II. The communication between the board and Quartus® Prime is via a download cable used for programming, such as the Intel® FPGA Download Cable II
- Observation signals are monitored via the FPGA's JTAG pins
- No need to reserve user I/O pins for debugging!
- No need for external devices such as a logic analyzer or oscilloscope!
- Free of charge!
Let's get ready!
To run the Signl Tap locig analyzer on an FPGA, you will need
Board with FPGA |
Target devices Intel® Agilex series / Stratix® series / Arria® series / Cyclone® series / MAX® 10
|
Development Software |
Quartus® Prime Pro Edition / Quartus® Standard Edition / Quartus® Lite Edition
|
Download Cable |
Intel® FPGA Download Cable II (formerly USB-Blaster™ II)
|
What kind of work is involved?
There are only 4 steps!
Step 1 |
Step 2 |
Step 3 |
Step 4 |
Create Signal Tap IP |
Implement the Signal Tap IP in the user design Implement Signal Tap IP & Compile |
Download .sof to FPGA |
Sampling Data Acquisition and observation of sampling data |
Note that the user design for the Signal Tap must have been synthesized or placed and routed in advance.
1. Creating Signal Tap IP
Create a new STP file. IP can be created by setting conditions on this sheet.
Specify the sampling clock
In the Signal Configuration window, select the clock for the Signal Tap to operate from the user circuit.
The Signal Tap samples the monitor signal at the rising edge.
As with a normal logic analyzer, the observation accuracy of the monitor signal depends on the frequency of the sampling clock.
The clock can be supplied separately from an external FPGA.
Please refer to the following document for how to use Node Finder. (Please search for "Node Finder" as a keyword.)
Quartus® Prime - Assignment Editor
Select the signal to be monitored.
Select the signal to be observed using NodeFinder. The selected signal can also be used for the trigger condition. However, signals specified as sampling clocks cannot be monitored.
Hanako's Little Tips
There is a way to register the internal signals to be observed in the STP file without using Node Finder.
It is to use Technology Map Viewer!
You can select signals visually and register them easily. This is the method I recommend.
For more details, please refer to this article.
How to easily register internal signals you want to capture with Signal Tap into STP files
Set trigger conditions
Select a condition for the signal you want to use as the trigger condition.
2) Implement and compile Signal Tap IP in your design
Select File menu > Save As on the STP file to name and save the STP file.
The message "Do you want to enable Signal Tap File "filename.stp" for the current project? (The following figure shows how to confirm).
This completes the implementation of Signal Tap! There is no connection work by code at all.
After that, click the icon on the STP file to compile the user design including the Signal Tap IP.
3. download .sof to FPGA
In the JTAG Chain Configuration window in the STP file (top right), select the download cable and confirm the sof file to be transferred. Then, click the Program Device button to start downloading.
4. sampling data acquisition and observation
Click the Run Analysis button to display the latest sampling data that hit the trigger event in the STP file.
If you just want to change the high or low of a trigger condition, there is no need to recompile.
Just click the Run Analysis button immediately after changing the value.
See, it's that easy!
If you just want to observe the internal signals of the FPGA, you can easily debug with Signal Tap without having to pull out a large piece of equipment such as a logic analyzer.
Hanako's little point
Recompilation of Signal Tap IP after implementation may increase the compilation time and affect the layout. (The Lite Edition does not support incremental compilation and cannot be used in conjunction with Quartus Prime.)
During debugging, any changes that affect the circuit configuration of the Signal Tap IP, such as adding or removing instances of the Signal Tap, adding or removing signals to be sampled or used for trigger conditions, or changing the sampling clock, will require recompilation.
For more information, see the following documents:
Design Debugging with the Signal Tap Logic Analyzer (Quartus Prime Standard Edition)
Design Debugging with the Signal Tap LogicAnalyzer (Quartus Prime Pro Edition)
Finally
In this article, we introduced the Signal Tap Logic Analyzer.
If you want to be one of the first to try out the Signal Tap Logic Analyzer functionality, you've come to the right place!
The following tutorials, sample designs, and supported evaluation and development kits will give you a quick experience of the workflow from creating Signal Tap IP to debugging it on the device. We hope you will find them useful.
Tutorial : Documentation
quartus_signaltap_tutorial_v1710_r1__1.pdf
Tutorial: Sample Designs for the Cyclone® 10 LP FPGA Evaluation Kit
Tutorial: Example Designs for MAX® 10 FPGA Evaluation Kit
Tutorial: Design-Only Projects
To be able to use SignalTap® II (now Signal Tap) with Quartus® Prime Lite Edition 16.0 or earlier, a "spell" is required.
The spell is to enable the TalkBack feature!
Follow the steps below to enable the TalkBack function.
1. Select Tools menu ⇒ Options.
2. In the Options window, select Internet Connectivity from the Category.
3. In the Internet Connectivity dialog window, click the TalkBack Options button.
4. In the TalkBack Options window, tick (On) the Enable sending TalkBack data to Altera option.
That's all there is to it!
[Related FAQs] What is the TalkBack feature?
Recommended Documents
Quartus® Getting Started Guide - Using the Signal Tap Logic Analyzer