This three-part document describes how to achieve DMA transfers using the PCI Express (PCIe) hardware IP on the FPGA.
This document is illustrated using the Cyclone® V GT FPGA Development Kit.
Basics
This document provides verification results of DMA transfers using a reference
design that implements the Avalon-MM interface-enabled PCI Express hardware
IP.
It describes the sequence of steps from design download, implementation,
and operation verification to transfer rate verification.
Document "Basics (Rev.2)
Hardware Edition
As an application of the Basic Edition, this document introduces how to implement
various peripherals such as memory controllers on Platform Designer.
Software for transfer rate measurement running on a PC and detailed mechanisms
during read/write and DMA transfers to the target using Signal Tap Logic Analyzer are
also explained. The software is available in the following formats: ELS1362_S000_S
Document "Hardware Edition (Rev.3)
ELS1362_c5gt_gen2x4_mSGMDA__2.zip
Reference Design "Hardware Edition
Software Edition
This is a sequel to the Basic and Hardware Editions, and introduces how to
access the design of the Hardware Edition from the Windows® environment.
It explains the environment and methods for creating simple device drivers
based on simple software, as well as the results of verification using actual
devices.
Document "Software Edition (Rev.1)