Hello, my name is Altera Hanako.
My name is F. Hanako and I am a technical support engineer for Altera FPGA products at Macnica.
When performing functional simulation with ModelSim* - Altera FPGA Edition (hereafter referred to as ModelSim - AFE), I would like to reference (monitor) signals at the Altera FPGA pin level, but I would also like to reference the internal signals of the FPGA at the same time, right? How can we do this?
The following methods are available to display the FPGA internal signals in the Wave window during simulation.
[A] Describe and display them in the testbench
[B] Displaying by GUI operation of ModelSim - AFE
In this article, we will introduce [A] method to describe and display in a testbench (i.e., how to write a testbench to display internal signals of FPGA in the Wave window ).
Sample Design
The following figure shows a sample design displayed in Quartus Prime's RTL Viewer.
The lower module of this design is taps (instance name: taps_inst).
In this article, we will use the case of referencing the output of register xn_1 (7bit) inside taps as an example.
Note that the instance name of the highest-level module of the FPGA in the testbench is fpga.
How to Write a Testbench
How to write a testbench to monitor the internal signals of your design depends on your language.
For Verilog HDL users, see here.
For VHDL users, see here.
Even if Verilog HDL and VHDL are mixed in the lower hierarchy, they can be referenced using this method.
How to write Verilog HDL
In Verilog HDL, there is a general way to reference internal signals of lower-level modules.
Declare a local signal to reference an internal signal with wire, and delimit the hierarchical path to the desired signal with "." (dot). (dot).
The hierarchical path is specified using instance names.
For example, to reference the output of register xn_1 in taps:taps_inst, write
wire [7:0] moni = fpga.taps_inst.xn_1;
moni is the name of the signal to which the referenced internal signal is connected, and the name is user-defined.
How to write VHDL
VHDL does not have a syntax for internal references like Verilog HDL.
However, in ModelSim* (including ModelSim* - Altera FPGA Edition), the Signal Spy feature can be used for this purpose!
In VHDL, add the following util package (modelsim_lib library) to your testbench
library modelsim_lib; use modelsim_lib.util
use modelsim_lib.util.all;
Then, a local signal to refer to the internal signal is added with a signal declaration and specified with init_signal_spy using the process statement.
init_signal_spy (src_object, dest_object,verbose);
src_object: Hierarchical path of the referenced signal
dest_object: Hierarchical path of the signal name to which the referenced signal is connected
verbose: message output; 1, no output; 0
The hierarchical path is specified using instance names.
For example, to reference the output of register xn_1 in taps:taps_inst, write as follows
moni is the name of the signal to which the internal signal to be referenced is connected, and the name is user-defined.
architecture bench of top_tb is
...
signal moni : std_logic_vector (7 downto 0);
...
begin
... begin
monitor : process
begin
init_signal_spy("/fpga/taps_inst/xn_1", "/moni", 0);
wait;
end process monitor;
...
In this article, we have shown how to write a testbench to monitor the internal signals of a design.
This description will improve the efficiency of your simulation work! Try it!
Recommended articles/documents are here
FPGA Functional Simulation with NativeLink
Let's try it for the first time! Test Bench
ModelSim® - Altera FPGA Edition - RTL Simulation Method
Altera® FPGA Development Flow / FPGA Top Page