Hello, I am Shiwshiw, my training period is over and I have been assigned to the Memory Team.
In order to gain knowledge about memory, I had been perusing memory-related articles written by senior members of the team in the past.
Through training, reading past articles, and studying memory, I found out that the data transfer method between FPGA-memory and inside FPGA is different.
How can data be processed successfully with different data transfer methods? So this time, I investigated the data transfer method between FPGA and memory.
1. data transfer method between FPGA and memory - SDR and DDR
As mentioned at the beginning of this article, the data transfer method between FPGA and memory is different from that inside the FPGA.
The FPGA transfers data using the SDR (Single-Data-Rate) method, which transfers data only at the rising edge of the CLK.
On the other hand, data is transferred between the FPGA and memory using the DDR (Double-Data-Rate) method, which transfers data on both the rising and falling edges of CLK.
FPGA internal data transfer method: SDR (Single-Data-Rate)
Data transfer method between FPGA and memory: DDR (Double-Data-Rate)
One question arises here.
If data is transferred from memory to FPGA using the DDR method, which can process data on the rising and falling edges of the CLK, won't the FPGA still be able to process the data since the SDR method only transfers data on the rising edge of the CLK?
I immediately asked my senior.
Shiwshiw "Can data transferred from memory in DDR mode be processed in an FPGA in SDR mode?"
Senior "FPGAs can do parallel processing, so they can.
I had forgotten that FPGAs are capable of parallel processing.
So how is data transferred from memory in DDR format processed in an FPGA?
2. Processing DDR data in an FPGA
The following figure shows the processing of DDR data in an FPGA (Figure 1) and the timing diagram of data and clock (Figure 2), as well as the abbreviations.
| Abbreviation | Abbreviation Description |
| DATA_IN | Data transferred from memory to FPGA by DDR |
| DATA_IN | CLK shifted by 90° phase |
| NOT_Inclock | NOT of Inclock |
| REG_OUT | DATA_IN is taken at the timing of the rising edge of NOT_Inclock, and the data output |
| DATA_OUT_1 | DATA_OUT_1 DATA_IN is taken at the timing of the rising edge of Inclock, and the data is output. |
| DATA_OUT_2 | REG_OUT is taken at the rising edge of Inclock and data is output. |
| Data A | Data transferred at the rising edge of CLK in DATA_IN (red letter A in Figure 2) |
| Data B | Data transferred on the falling edge of CLK in DATA_IN (blue letter B in Figure 2) |
Figure 1 Processing of DDR data by FPGA
Figure 2 Data and Clock Timing
To enable the SDR to process the data transferred by DDR
【1】First, phase shift CLK by 90° (CLK → Inclock).
【2】 Next, DATA_IN is taken at the timing of the rising edge of Inclock, resulting in an output like DATA_OUT_1, which outputs only data A.
【3】 Also, if DATA_IN is taken at the timing of the rising edge of NOT_Inclock, the output will be like REG_OUT, and only data B will be output.
【4】 By taking the REG_OUT output by 【3】 at the timing of the rising edge of Inclock, DATA_OUT_2 (data B) is output at the same timing as DATA_OUT_1 (data A).
Thus, by using the 90° phase shift of CLK and NOT, and by dividing the rising and falling data into two systems and processing them in parallel, it was found that data transferred in DDR format can be converted to SDR format and data can be processed normally inside the FPGA.
I would like to utilize the knowledge of FPGA and memory data transfer methods that I have learned this time to respond to inquiries about timing analysis and timing design.
Summary
The method that transfers data only at the rising edge of CLK is called SDR (Single-Data-Rate), and the method that transfers data at both the rising and falling edges of CLK is called DDR (Double-Data-Rate).
The SDR method transfers data inside the FPGA, while the DDR method transfers data between the FPGA and memory.
Data transferred from memory in DDR format is converted to SDR format inside the FPGA and processed in parallel.
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