Hello, my name is Altera Hanako.
My name is Altera Hanako and I am the technical support for Altera® FPGA products at Macnica.
Quartus® Prime Pro Edition, the development software for Altera FPGAs, has two file conversion tools for FPGA configurations.
Both conversion functions take a .sof for FPGA as input file and convert it to an output file format appropriate for the configuration memory used.
Each file conversion tool supports different FPGA families.
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FPGA
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File Conversion Functions |
|
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Programming File Generator |
Convert Programming Files |
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Agilex® 7 Stratix® 10 |
✔ x |
×x |
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Arria® 10 Cyclone® 10 GX |
×x |
✔ |
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Remarks
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Features supported since Quartus Prime Pro Edition 18.0
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Features previously used in Pro and Standard Editions (seethiscontent for operation) |
The Quartus® Prime Pro Edition Programming File Generator also supports MAX® 10 and Cyclone® 10 LP.
This section describes how to generate .pof / .jic / .rpd files for configuration memory using the Programming File Generator.
Operation Procedure 1.
1. start Programming File Generator
2. select FPGA family and configuration mode
3. select file format to generate
4. set .sof
5. select configuration memory (only for .pof/.jic generation)
6. Select FPGA to transfer Serial Flash Loader (only for .jic generation)
The following is a concrete explanation of the screen operations. 1.
Start Programming File Generator
Select File menu > Programming File Generator to launch the GUI. 2.
Select FPGA family and configuration mode
Select the appropriate FPGA family and configuration mode.
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Item |
Overview |
Choice |
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Device family
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Specify the FPGA family to be configured.
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Agilex, Stratix 10, Cyclone 10 LP, MAX® 10 Cyclone 10 LP, MAX® 10 |
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Configuration mode
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Specify the configuration mode.
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Active Serial x4, AVST x8, AVST x16, AVST x32 AVST x8, AVST x16, AVST x32 3. |
Select the file format to be generated
In the Output Files tab, select the folder, file name, and file format for the output files.
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In the Output Files tab, select the folder, file name, and file format for the output file. |
Summary |
Choice |
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Output directory
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Specify the folder where output files will be saved.
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Optional
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Name
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Specifies the name of the output file.
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Optional
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Select the format of the generated file.
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Set .sof
In the Input Files tab, click the "Add Bitstream" button and select the .sof file for the target FPGA.
After selecting the file, highlight the sof file part and click the [Properties] button. Here you can configure security options and Bootloader settings.
The Compression function is automatically set to On.
Add more options as needed.
(Left) When .pof or .jic is selected / (Right) When .rpd is selected
To generate the rpd file, click the "Generate" button to finish the process.
To generate a pof file and a jic file, proceed to the next operation5. 5.
Select configuration memory (only for .pof/.jic generation)
On the Configuration Device tab, click the "Add Device" button to specify the configuration memory.
(left) when .pof is selected / (right) when .jic is selected
Next, highlight the selected configuration memory, click the [Add Partition] button, and specify the sof file set in step 4 and the page number to be stored.
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Item |
Summary |
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Name
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Name the configuration file with an arbitrary name.
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|
Input file
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Selects the sof file set in operation 4.
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Page
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Specify the page to store the sof file.
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Address
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Specify the address if necessary.
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To generate a pof file, click the "Generate" button to finish the operation.
To generate a jic file, proceed to the next step 6. 6.
Select the FPGA to which the Serial Flash Loader is to be transferred (only when generating .jic files).
[Click the "Select" button to select the FPGA to which the Serial Flash Loader (SFL) is to be transferred.
Click the [Generate] button to finish the process.
Recommended Articles/Documents
Altera® FPGA Development Flow / FPGA Top Page
Quartus® Guide - Generating and Converting Programming Files (Convert Programming Files)