Hello, my name is Intel F. Hanako.
My name is Intel F. Hanako and I am the technical support for Intel® FPGA products at Macnica.
For RTL-level functional simulation of designs containing IP for Intel FPGAs using EDA simulators, we recommend using Quartus® Prime's NativeLink simulation flow, but Quartus Prime Pro Edition does not support NativeLink simulation.
Table 1: NativeLink Simulation Support in Quartus Prime
| Quartus Prime Pro Edition | × |
| Quartus Prime Standard Edition | 〇 |
| Quartus Prime Lite Edition | × |
If your design includes IP, it is not easy to run because you need to set up a simulation model (library) for the IP in addition to the simulation model (library) for the Intel FPGA.
Therefore! Here it is
We will show Quartus Prime Pro Edition users how to perform RTL-level functional simulation of a design that includes IP.
We will use Questa* - Intel® FPGA Edition (hereafter referred to as Questa - IFE, including Starter Edition), Questa and ModelSim as simulation tools.
For other EDA simulators, please refer to the following documents
Intel Quartus Prime Pro Edition User Guide: Third-party Simulation
Target Software Environment
| Supported Quartus Prime Editions | Quartus Prime Pro Edition |
|
This content covers Simulation tools (*1) |
Questa - Intel FPGA Edition (including Starter Edition) (*2) or Questa, ModelSim |
*1: Please refer to the release notes of the Quartus Prime version you are using for the supported versions of each EDA tool.
*2: Please use the one that is compatible with Pro Edition.
Generate Simulation Models of IP
In order to simulate IP at the RTL level, it is necessary to generate a simulation model for the IP.
When creating IP in IP Catalog or Platform Designer, specify the language in the Generation dialog box that pops up when you run Generate HDL, and select the "Create simulation model option to specify the language and select the corresponding tool to generate a script to run the simulation.
Then click the Generate (or Generate HDL) button to generate a function model and script file for the simulation tool for that IP.
Workflow
The following is a workflow of a design containing IP generated with Quartus Prime Pro Edition and then run through
Questa - IFE (or Questa or ModelSim) for RTL level simulation.
It is assumed that the Quartus Prime project has already been created and the design is complete.
1. Register your design in the Quartus Prime project
2. generate simulation scripts for IP
3. Create a simulation script including the user design 4.
4. Run the simulation
1. Register your design in the Quartus Prime project
Register your design in the Quartus Prime project, which Quartus Prime will need at compile time.
For IP designs, register the *.ip file.
Project menu > Add/Remove Files in Project 2.
2. generate simulation scripts for IP
The following menu allows you to generate simulation scripts for all IP registered in the Quartus Prime project.
Tool menu > Generate Simulator Setup Script for IP
The path to the currently open Quartus Prime project folder is displayed by default.
For file management, it is recommended to prepare a separate folder for script files and generate them there.
(In the above figure, the sim_script folder is created in the Quartus Prime project C:/fpga_design and the script files are generated there. 3.)
3. Create a simulation script including user design
1) Open msim_setup.tcl in the mentor folder in the folder generated in step 2 with a text editor.
# # TOP-LEVEL TEMPLATE - BEGIN
From.
# # TOP-LEVEL TEMPLATE - END
Copy and paste all lines from # # TOP-LEVEL TEMPLATE - BEGIN to # # TOP-LEVEL TEMPLATE - END into a new text file.
Then, name the file mentor.do (the file name is arbitrary) and save it in the same folder as msim_setup.tcl.
2) Delete the first two characters (# and space) of each line.
3) Edit the contents of the script to match the folder environment.
The commands are explained from above.
set QSYS_SIMDIR <script generation output directory
Specify the folder path (absolute or relative) of the IP simulation script generated by Quartus Prime.
In other words, the path specified in Generate Simulator Setup Script for IP.
In this example, the sim_script folder is relevant.
Example) set QSYS_SIMDIR . /
Hanako's Point 1)
When setting a relative path, the reference folder is the working folder of Questa - IFE, and by default, the folder specified in Generate Simulator Setup Script for IP is assumed to be the working folder of Questa - IFE. If the working folder of Questa - IFE is to be a separate folder, QSYS_SIMDIR should be set to the path specified in Generate Simulator Setup Script for IP, considering the working folder of Questa - IFE as a reference. If you specify a relative path, please note this point.
source $QSYS_SIMDIR/mentor/msim_setup.tcl
Load the script for IP simulation.
No editing is required.
set USER_DEFINED_COMPILE_OPTIONS <compilation options
set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL
set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
Set compile options as needed.
Since this is not used in this case, enter # at the beginning of the line and comment out.
dev_com
Compile a standard simulation model for Intel FPGAs.
No editing is required.
This command is executed on Questa and ModelSim, which are not Intel Edition.
Questa - IFE users do not need to comment out this command, because it is automatically detected as Quetsa - IFE and is not executed.
com - Compiles a simulation model of the IP.
Compiles the IP simulation model.
No editing is required.
vlog <compilation options> <design and testbench files
Add the command to compile all user design and testbench files except the IP design.
The vlog command is a compile command for Verilog HDL source.
VHDL users edit to vcom.
e.g.) vcom <compilation options> <design and testbench files>.
<compilation options> : You can set options at compile time if needed.
For example
You can specify the language version and the name of the folder and library where the compiled results will be stored.
vcom -2008 -work work . /simple_counter.vhd
vlog -vlog01compat -work work work . /simple_counter.v
For more information on the options, see vlog or vcom in the Commands chapter of the Command Reference Manual for each simulator tool.
<design and testbench files>: Specify the path (absolute or relative) of files to be compiled.
Hanako's Tweet (1)
Command Reference Manual is stored in the Questa - IFE installation folder.
Example) \\<tool_install_dir>\docs\pdfdocs\questa_sim_ref.pdf
set TOP_LEVEL_NAME <simulation top
Sets the top-level testbench module/entity name.
This command is used by elab / elab_debug command to elaborate the top level.
Example) set TOP_LEVEL_NAME top_sim
set USER_DEFINED_ELAB_OPTIONS <elaboration options
Set elaboration options as needed.
Since it is not used in this case, enter # at the beginning of the line and comment out.
elab_debug
The vsim command will be executed with -voptargs=+acc (an option to enable visibility to objects in the optimized design) applied.
If you do not want to have optimization, use the following command
elab
VHDL users can specify Resolution by adding the -t option after the elab_debug or elab command.
Example: elab_debug -t 1ps
Resolution If none is specified, the command is processed as ns.
Verilog HDL users depend on Resolution described in the testbench.
Hanako's Point 2)
To display simulation results as waveforms, append the add wave command before the run command.
To register all ports on the testbench, * (asterisk) is OK!
Example) add wave *
run -a
Runs the simulation.
-a is equivalent to -all. Runs for the time specified by the testbench.
If you want to specify a time, specify a space after the run command, followed by the time and the unit.
Example: run 500ms
exit -code 0
This is not necessary in this case, since we are using the GUI. Enter # at the beginning of the line and comment it out.
After editing, save the do file. 4.
4. run simulation
(1) Start Questa - IFE.
(2) Specify the working folder for simulation by selecting "File" menu > "Change Directory".
In this case, it is C:/fpga_design/sim_script.
(3) Select Tools menu > Tcl > Execute Macro and select the do file created in step 3 by double-clicking it.
(4) The contents of the script will be executed and the simulation results will be displayed as waveforms in the Wave window.
Hanako's tweet (2)
If the design (including testbench and IP) is changed after the simulation is executed, the source code must be recompiled and the simulation rerun. To do so, enter # at the beginning of commands in the do file created in step 3 that do not need to be re-run, comment them out, and reuse them. (For example, dev_com).
This will eliminate duplicate work and reduce your man-hours slightly.
With these tips, you can easily simulate functions in Pro Edition as well!
Recommended articles and documents
FPGA Functional Simulation with NativeLink
The Chef’s Whimsical Test Bench – A Secret Recipe for Efficiency