Hello. My name is Ume Onigiri. I studied the full compilation flow of Intel® Quartus® Prime development software at a training course. Here is the flow.
I could understand what is done in each process, but I can't get an image of logic synthesis and place-and-route. Therefore, this time we will study logic synthesis and place-and-route.
Logic synthesis is the optimization of circuits written in HDL or Block Diagram / Schematic File. Let's take the following figure as an example.
If you look at Figure 1 carefully, you can see that the area circled in blue is useless. This means that resources are also wasted. Logic synthesis eliminates such waste of logic, and the result of actual logic synthesis of Figure 1 with Quartus II is shown in Figure 2. Here, the blue circled area is treated as a simple wire.
Incidentally, on Intel® Quartus® Prime, you can perform logic synthesis by clicking the button shown in the figure below or by clicking Start in the processing menu and selecting Start Analysis & Synthesis.
Place and Route is to determine how to place and route the synthesized circuit on the actual device. The following figure shows an example.
As shown in the figure below, an FPGA consists of many logic elements (LEs) and the interconnections between them. Depending on the design size, a large number of LEs are used to realize the circuit after logic synthesis. The placement and routing determines where the LEs are placed and how they are connected.
In addition, Intel® Quartus® Prime has a feature called Chip planner that graphically displays the placement and routing results. This allows the user to see which LEs are used and how they are routed.
Incidentally, on Intel® Quartus® Prime, you can even perform placement and routing using Start Fitter from the Start menu in the processing menu.
Until now, I had been performing logic synthesis and place-and-route without understanding what I was doing, so I sometimes wondered "Is everything OK?" I sometimes wondered if it was safe.
But now I understand what is being done in logic synthesis and place and route.
I would like to continue to introduce more and more things that I did not understand during the training.
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