Hello, this is Tot.
In the previous article, I explained that the reason why the data change points of asynchronous counters have different timing for each bit is that each register takes different time to reach the clock input.
This time, we will explain that asynchronous circuits are not suitable for FPGA design because the output timing of each register does not match.
Asynchronous circuits are not suitable for FPGAs!
In asynchronous counters, the clock input to each register uses the signal output from the previous register. Therefore, in some cases, the edges of each clock do not have the same timing.
The cause of this difference in clock edges is wiring delay, as mentioned earlier.
Why Clock Edges Do Not Have the Same Timing
Wiring delays depend on where the registers generating the clock are placed on the FPGA device and which wiring is used.
Since the delay due to clock routing between each register is not the same value, there will be a difference in the change point of the output data.
In a counter, a difference in the clock edge driving each register results in a difference in the point of change of the data.
This difference in the change point of the output data results in a smaller range of valid data, which reduces the timing margin.
As a result, circuits that require high-speed operation may not achieve their timing constraints.
The faster the clock operating frequency, the more difficult it is to achieve an asynchronous counter.
Conclusion
･Asynchronous counters have a clock delay that affects the circuit.
･Asynchronous counters cannot achieve their timing constraints because the higher the operating frequency of the clock, the greater the delay.
･Asynchronous counters do not have a constant clock delay.
Therefore, I understood that synchronous circuits should be used in FPGAs, where there is a degree of freedom in placement and routing.
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