Hello, my name is Altera Hanako.
My name is Altera Hanako and I am the technical support for Altera® FPGA products at Macnica.
MAX® 10 is a non-volatile FPGA. It has a built-in flash memory (CFM) for configuration, so no external configuration memory is needed.
In this article, we will introduce a slightly different use of the CFM, "dual configuration.
Overview of Dual Configuration
The MAX® 10 CMF can store up to two compressed configuration images that can be switched between during operation. This configuration is called "dual configuration.
(However, to store two images on the device, the compression ratio must be greater than 30%.)
MAX® 10 offers three types of functional options: "compact," "flash," and "analog.
Of these, only "Flash" and "Analog" support "Dual Compressed Image" as a configuration mode. only "Flash" and "Analog" support "Dual Compressed Image" as a configuration mode.
(However, the flash type is not commonly used in WLCSPs (wafer level chip scale packages), so it is effectively "analog only.")
The MAX® 10 CFM consists of three sectors, CFM0/CFM1/CFM2. (The 10M02 has only CFM0.)
CFM0 is used as the area for configuration image 0, CFM1 and CFM2 are used as the area for configuration image 1.
Dual configuration uses the CONFIG_SEL pin of the MAX® 10 to select the image. The device externally supplies a High or Low to the CONFIG_SEL pin, and the state of this pin when the MAX® 10 is powered up or at the start of reconfiguration determines which image is configured.
★ References (from Device Pin Connection Guidelines )
"MAX 10 FPGA Device Family Pin Connection Guidelines"
Let's get ready!
To achieve dual configuration with MAX® 10, the following are required
A development board with a MAX® 10 device (with flash or analog functionality options)
For example, theOdyssey MAX® 10 FPGA Eva Kit (Odyssey) or the MAX® 10 FPGA Development Kit can be used. (*An absolute requirement for board selection is that the input to the CONFIG_SEL pin be switchable between High and Low.)
Download the appropriate cable for the development board you are using.
In case of Odyssey, it is easier to use USB-Blaster™ or USB-Blaster™ II. (Even if you don't have one, you can use a microUSB cable.
For the MAX® 10 FPGA Development Kit, you can use the USB-Blaster™ or USB-Blaster™ II, or the Embedded USB-Blaster™ II with the included miniUSB cable .
Quartus® Prime Lite Edition (Pro/Standard Edition also acceptable)
MAX® 10 can be developed with free tools.
Two types of design projects for your development board
If you want to experience the workflow first hand, you can use the sample designs for dual configuration!
Get a free FPGA sample design from the Design Store.
Click here to get Odyssey's dual configuration sample project for Quartus® Prime 16.0.
Get the MAX® 10 FPGA Development Kit dual configuration sample project for Quartus® Prime 16.0 here.
Let's do it for real!
To give you a quick idea of what you need to do, you just need to merge the SOF files of the two projects, but you don't just need to match them up. In the design of each project, we will incorporate the IP for dual configuration (available for free).
The process is as follows.
1. include the IP for dual configuration in the design
2. set options for dual configuration
Compile and generate SOF
Create POF files from the SOF files of the two projects 5.
Download POF to MAX® 10 device and verify operation 6.
Switch inputs to CONFIG_SEL and verify operation
Incorporate the dual configuration IP into the design
Incorporate the dual configuration IP into the top level of each project design.
First, open one of the projects and create the IP.
Tools menu > Qsys and double-click "Altera Dual Configuration" in the IP Catalog (upper left corner of the screen).
The Parameter Setup screen will appear. Set the frequency of the clock to be supplied to this IP (e.g., Odyssey's clock frequency is 1.5 MHz). (For example, set the frequency to 50MHz for Odyssey, and set the frequency for the MAX® 10 FPGA Development Kit, which has 4 different clock frequencies to choose from.) The maximum frequency that can be set is 80MHz.
Click on the Finish button to add it to the Qsys system.
Connect the clock (clk) and reset (nreset) ports of the dual configuration IP as shown below.
Set the clock frequency of the Clock Source (default name clk_0) to the same value as the clock frequency of the Altera Dual Configuration that has just been set.
In the Qsys File menu > Save As, specify the IP name and save folder.
Click the Generate HDL button at the bottom right of the screen to display the Generation dialog box, and specify the HDL language (Verilog/VHDL) to be generated for logic synthesis.
Confirm the path to the Output Directory and click the Generate button in the lower right corner of the screen.
Click the Close button, then the Finish button to close the window. Close the window by clicking on the Close button, followed by the Finish button.
When a message appears asking you to add the .qip file to the project, click the Add button to add the .qip file stored in the synthesis folder of the folder where the IP was generated from the Add/Remove Files in Project menu (Project menu).
Then add the Altera Dual Configuration IP to the top-level design in the project, and connect the clock and reset (Low active). Save the design after editing is complete.
Set options for Dual Configuration support
In Device and Pin Options (Assignments menu > Device), set various options.
[General Category]
Enable CONFIG_SEL pin option = ON.
[Configuration Category] ・Configuration Scheme : Internal
Configuration Scheme : Internal Configuration
・Configuration Mode: Dual compressed Images
・Generate compressed bitstreams option : ON
After setting, close all dialog boxes with the OK button. 3.
Compile and generate SOF
Double-click Compile Design in the Tasks window located at the lower left of the Quartus® Prime screen to execute and complete compilation. Then, close the project.
Do the same steps 1-3 for the other project. 4.
Create a POF file from the SOF files of the two projects
In Quartus® Prime, go to the File menu > Convert Programming Files and make the following settings.
[Output programming file].
Programming file type: Programmer Object File (.pof)
・Mode: Internal Configuration
・File name: Specify the file name and save folder for the POF file to be created
(Set Options/Boot/info options as necessary. info option if necessary)
[Input files to convert]
Select SOF Data and click Add File button.
Select the SOF file of the project to be written to CFM0 in Page_0. Select SOF Data in the lower row, and click Add File button.
Click the Generate button and the POF file will be created with the message "Generated file name.pof successfully".
Close the window with the Close button. 5.
Download the POF to the MAX® 10 device and verify operation.
Before writing the POF file, check and set the status of the CONFIG_SEL pin.
Note that the Odyssey and MAX® 10 FPGA development kits have a DIP switch to switch the CONFIG_SEL pin between pull-up and pull-down.
Now let's write the POF file to the MAX® 10 CFM.
After preparing the board, download cable, etc., start the Tools menu > Programmer and make the following settings.
Hardware setup: Select the download cable to be used
- Mode: JTAG
- Add File button: Select the created POF file
- Program/Configure option: ON
Note: If you do not see the name of the USB-Blaster™ family in the Hardware Setup...
Try to install USB-Blaster™ II driver
Let's try to install USB-Blaster™ driver
What to do if you cannot install USB-Blaster™ and USB-Blaster II drivers on Windows 10
Click "Start" button to start writing!
When the progress bar shows 100% and the message "Successfully performed operation(s)" is displayed in the Messages window, writing is complete.
Turn off the board and disconnect the download cable. Then turn on the board power again!
You can confirm that CFM is selected according to the state of CONFIG_SEL on the board and the image stored in it is configured and operating.
The image on the right shows the design in operation with image 0 selected and LED0/LED1 blinking alternately.
(Sorry for the still image.) 6.
6. switching the input to CONFIG_SEL and checking the operation
Next, let's switch the state of CONFIG_SEL.
Then either power the board back on (OFF to ON) or pull the nCONFIG pin low for more than a certain pulse width to reconfigure the MAX® 10 with power on, then supply it high again.
Odyssey has the nCONFIG pin pulled through a 10Ω resistor to The Odyssey has its nCONFIG pin pulled up to 3.3V through a 10Ω resistor, so it must be turned on again.
The other image has been configured and is operating.
The image on the right shows that image 1 is selected and the design is working with LED6/LED7 blinking alternately.
(Sorry, this one is also a still image.)
In the case of the MAX® 10 FPGA Development Kit, there is a push button (PB) on the nCONFIG pin, which is convenient because pressing this PB supplies a Low pulse to nCONFIG, allowing reconfiguration to be performed without turning the board power off.
This completes the MAX® 10 dual configuration system...
I hope you all enjoy the experience.
The development board and download cable that appeared in this issue can be purchased here, so you can experience it right away.