Hello, my name is Ume Onigiri. I created a 4 bit counter in a Verilog HDL training course. Here is the program.
I designed it to count up "0001" each time the clock starts up. To check if it works as required, I created a test bench and ran a simulation in ModeleSim®-Altera. The clock period was set to be 20 ns. Here is the result of the simulation.
The output is indefinite. Why is this? Let's review the program again.
It is true that the program is written so that "0001" is added to count at the rising edge of the clock cycle. But here is something I noticed. The original value of count is not determined at the first rise of the clock, so "0001" cannot be added to count and it is indeterminate. Yes, we can set the initial value of count.
So I rewrote the program as follows.
The rewritten part is the red underlined part in line 6. I defined the initial value of count in this description. And here is the result of the simulation. This time, I was able to observe the output counting up.
Intel's CPLD/FPGA is designed so that the initial value of the register is "0" after startup. In memory blocks implemented as RAM, the initial value is "0" if the initial value is not defined in a .mif or .hex file during logic design (for memory blocks implemented as ROM, it is essential to define the initial value).
Therefore, when performing logic synthesis or placement and routing with Intel® Quartus® Prime development software, there is no problem because the device operation is not affected even if the initial values are not written.
However, when performing simulation, if initial values are not defined as necessary, waveforms may not emerge properly.
Therefore, I realized that it is important to properly check if the initial values are defined before performing simulations.