Hello, my name is Masuo.
Starting this week, I will be writing a series of articles on "timing analysis." The most difficult part of the training for newcomers was the lecture on timing analysis. Through this column, I would like to summarize the lecture materials and notes on timing analysis and show you what I stumbled upon.
Today, we will discuss SDC commands. Here is an example of SDC description in TimeQuest.
There are various SDC descriptions, but in this column, I would like to introduce the SDC description picked up in the training for newcomers.
Clock Constraints
Table 1. list of SDC commands for clock constraints
|
Command |
Description |
|---|---|
|
create_clock
|
Defines the clock frequency supplied by the clock pin.
|
|
create_generated_clock
|
Define the clock frequency supplied by internal logic and PLL
|
|
derive_pll_clocks
|
Defines the clock frequency supplied by the internal PLL. Convenience command to constrain all PLL outputs.
|
|
set_clock_uncertainty
|
Defines the clock rise/fall time variance. Allows the user to set their own constraints for the board.
|
|
derive_clock_uncertainty
|
Defines the clock rise/fall time variation. Variation model provided by Altera.
|
|
set_clock_latency
|
Defines the clock latency between the external device and the FPGA.
|
Figure 1 shows an image of the clock constraints for each command.
Figure 1. Image of clock constraints
I/O Constraints
Table 2. List of SDC commands for I/O constraints.
|
Command |
Description |
|---|---|
|
set_input_delay
|
Defines the delay time for input signals.
|
|
set_output_delay
|
Define delay time for output signal.
|
|
set_false_path
|
Exclude the specified path from timing analysis. Used for asynchronous paths (reset/clear signals), etc.
|
|
set_multicycle_path
|
Define analysis at any clock edge for each setup/hold.
|
The I/O constraints by each command are imaged in Figure 2.
Figure 2. Image of I/O constraints
As shown above, TimeQuest Timing Analyzer also analyzes the relationship between the external device and the FPGA. It does not perform a Close on the FPGA, but performs a timing analysis of the entire board!
Conclusion
TimeQuest Timing Analyzer analyzes the timing of the entire board.
New Engineer's Blush Blog Article List