Hello, I'm Tophu!
I would like to summarize the timing analysis that I struggled the most to understand throughout the year.
This article is a must read for FPGA beginners.
About a year ago, I took a training course on timing constraints and was able to understand the concept of timing constraints.
However, when it came to actually designing a circuit and applying timing constraints, I didn't know where to start.
Are these constraints correct? I was allergic to timing.
It was a senior colleague who gave me a prescription for my timing allergy.
In this article, I would like to explain the advice (constraint procedure) from a senior colleague that helped me overcome my timing allergy.
First, let's check the flow of timing constraints and analysis (Figure 1).
Figure 1: Flow of timing constraints and analysis
The first difficulty in this flow is the creation of the SDC file.
SDC constraints must be applied to all paths in the circuit.
It may seem difficult to apply constraints to all paths, but there is a specific order in which constraints are applied, and applying constraints according to that order makes it less difficult!
Figure 2 summarizes the order.
Figure 2. Order of SDC file description
From Figure 2, we can see that there are only two major types of commands required for constraints.
Please refer to this article for more information on timing constraint commands.
Since I/O constraints are based on clock frequency, we will first constrain the clock.
We will now apply the constraints to the circuit example. Assuming the circuit shown in Figure 3, we will apply constraints.
Figure 3.Schematic Example
counter:U1 counts up to the first place and counter:U10 counts up to the tenth place.
MS is an external signal to select whether to count up or down the counter.
In this circuit, there are two paths to apply "clock constraints": "input clock: CLK" and "PLL output clock".
First, we will constrain the input clock.
The create_clocks command is used for this.
If there is no SDC file, create a new one.
File → New → Synopsys Design Constraints File to create a new SDC file.
In this case, we will use a 50 MHz clock, so we will define a clock with a frequency of 50 MHz.
Using the GUI, you can easily generate commands.
Right-click in the SDC file where you want to enter the command → Insert Constraint → Create Clocks, and the GUI will appear. (Figure 4 and Figure 5 )
Figure 4. GUI for SDC constraint command generation
Figure 5. GUI usage screen
Clock name : Name of the clock to be constrained
It is not necessary to match the clock name in the design.
The clock name specified here is valid only in the SDC file (in this case, CLK is the same as in the design for clarity).
Period : Set the period of the clock.
50MHz clock, so enter 20ns for the period.
Targets : Establish the ports and pins to be constrained
Finally, select the targets, use get_port.
This can be used to search for a port name in the design, and as get_port {CLK} we apply the constraint create_clock to the port named CLK.
Set the constraints you want to give and finally click Insert to insert the command into the SDC file (Figure 6 ). (Figure 6 )
Figure 6. SDC after inserting the command
Next, constrain the PLL output clock.
This is done by entering the derive_pll_clocks command.
This command completes the constraint of the PLL output clock.
This completes the clock constraints and is shown in Figure 7.
Figure 7. Clock Constraints
By performing the above constraints, the red line in the circuit example (Figure 8 ) has been constrained.
Figure 8. Circuit diagram after applying constraints
When you constrain the clock, you are constraining the paths in the circuit area (clock domain) that are driven by the clock.
I used to think that I had to constrain every single path, so when I learned this, my barrier against timing constraints was lowered. (An image is shown in Figure 9.)
Figure 9 . Diagram of paths with clock constraints
I was able to input timing constraint commands and apply constraints to the I/O and false paths at this rate, and I felt that I was able to apply constraints more smoothly than when I was not so good at it.
For more information on I/O constraints, please refer to this article !
In addition
This time we used the derive_pll_clocks command to define the PLL output clocks.
If there are multiple PLL output clocks, there is a command to constrain them one by one.
It is the create_generated_clock command.
Figure 10 shows an example of using the create_generated_clock and derive_pll_clocks commands to apply the same constraints.
Figure 10 . Create_generated_clock command vs. derive_pll_clocks command
The derive_pll_clocks command is easier to write than the create_generated_clock command!
The create_generated_clock command can be used to place constraints on each output clock, which is useful when you want to verify the timing by changing the amount of clock shift, etc.
(With derive_pll_clocks, you have to start over from the design modification)
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