When creating a board that implements an Altera® FPGA, designers create a schematic by referring to the documentation published by the manufacturer.
This section will focus on the points to pay special attention to.
Quartus® Prime can also check the placement of devices based on their various constraints. Please use Quartus Prime to check the schematic in addition to the schematic check in the document.
Target FPGAs
Cyclone® V
Preparation
Here are some documents that you can refer to when creating your schematic.
| Pin Connection Guidelines | Schematic Review Worksheet |
| Cyclone® V Device Family Pin Connection Guidelines | Cyclone® V Device Schematic Review Worksheet |
Cyclone® V Overview (FPGA TOP)
The following diagram shows the pins that require special attention when designing the Cyclone® V board.
The placement of the pins in the figure is not related to the actual device.
Click each item to see the check points.
| MSEL pin | (3) Configuration pins | |
| (4) JTAG pin (5) Clock input pin | Clock input pins | (6) Other dedicated pins |
| Transceiver pins | DDR3 pin | HPS pin (⑨) |
| Dual-use pins | I/O pins | -I/O pins |
VCC, VCC for HPS, VCC for transceiver
| Apply the recommended power supply voltage by referring to the datasheet. |
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● Provide a measurement point near the FPGA. ● Provide a measurement point near the FPGA ● Be prepared to measure the power supply in case of a failure. |
| Refer to the Power & Thermal Design & Debug Guidelines |
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If all GXBs (transceivers) on the same side are not in use, use the following VCCE_GXBL and VCCL_GXBL can be connected to GND. |
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Number of decoupling capacitors Use the PDN tool as a reference for estimation. For more detailed estimation, use a dedicated tool. <Reference Power supply network (PDN) analysis tool Part 9 Confirmation and Review of Capacitance in FPGA Power Supply Design |
|
When configuring in Active Serial (AS) mode When configuring in Active Serial (AS) mode, VCCPGM should be 3.0 V or 3.3 V. |
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Power Supply Sequence For details, please refer to this document (Power-Up Sequence Recommendation for Cyclone V Devices). |
MSEL Pin
For MSEL pin information on Cyclone® V, please refer to the following.
| MSEL Pin Settings | Insert pull-up/pulldown resistor (1)(2) |
| Cyclone® V |
(see linked documentation) |
| Cyclone® V SoC via HPS |
(1) Weak Pull-Down Resistor (25kΩ) is inserted inside.
(2) If you want to switch configuration mode, use 0Ω resistor to switch to VCCPGM/GND.
See here for a list of MSEL pins.
Configuration pins
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DCLK Damping resistor insertion is recommended (minimum 0Ω) 10-50Ω In AS mode, take care of trace length (see document below) "Evaluating Data Setup and Hold Timing Slack in AS Configuration ". |
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● nCONFIG, nSTATUS Pull-up to VCCPGM via 10kΩ resistor |
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CONF_DONE Pulled up to VCCPGM via 10kΩ resistor Do not connect to LED as it is. - Do not connect to LED as it is ● Due to insufficient drive current, LED may not light up unless FET is applied. |
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If FPGAs are cascaded, pull up nSTATUS and CONF_DONE in common. INIT_DONE is pulled up individually (only if used) |
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nCE GND connection or pull-down through 10kΩ resistor This signal determines whether the FPGA is cascaded or not. |
| When nCEO is used, pull-up to VCCPGM via 10kΩ resistor |
JTAG pin
|
Check Point Insertion of a damping resistor with a 0Ω resistor is recommended for TCK. - To enable handling of cases where writing cannot be performed due to clock system trouble. |
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To enable handling of cases in which write cannot be performed due to clock system trouble. TCK: Pulled down via 1kΩ resistor (Pulled down via 1kΩ resistor even when not used) TDI : Pull-up to VCCPD via 1kΩ to 10kΩ resistor (When not used, pull-up via 1kΩ resistor) TMS : Pull-up to VCCPD through 1kΩ to 10kΩ resistor (Pull-up through 1kΩ resistor when not used) TDO : No pull-up/pulldown (Open when not used) |
| When cascading three or more FPGAs, insert buffers on the TCK and TMS lines. |
Clock Input Pin (5)
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When using single-ended clock, assign to p-channel. (The n channel does not directly ride on the global clock, which limits the use of the ALTCLKCTRL buffer.) |
| When using differential inputs, be careful of AC/DC coupling. |
| When using PLL, pull down the RREF_TL pin via a 2kΩ resistor (resistor accuracy is ±1%) |
⑥ Other dedicated pins
| Pin Name | Pin Name Comment |
| RREF_TL | Pull-down through 2kΩ±1% resistor |
| VREF | Connect to VCCIO or GND when not used as a dedicated pin |
Transceiver pin
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If the transceiver is not used, connect to GND. Clock (REFCLK_*) is connected to GND RX (GXB_RX_*, GXB_REFCLK_*) is connected to GND TX (GXB_TX_*) is floating. |
|
AC/DC coupling AC/DC coupling |
DDR3 pin
Check the following guidelines by referring to the following web contents.
Arria® V / Cyclone® V and DDR3 schematic check items (from Ultima Company technical contents)
Pins that are especially easy to mistake
- mem_reset_n
- mem_cke
- rzq
HPS Pin
| Cyclone® V SoC Pin Name | CLOCKSEL[1:0] CLOCKSEL[1:0 |
| CLOCKSEL[1:0] (1) | Pull-up to VCCIO voltage through 10kΩ resistor or pull-down through 1kΩ resistor |
| BOOTSEL[2:0] | VCCIO voltage pull-up across a 10kΩ resistor or pull-down across a 1kΩ resistor |
| HPS_nRST (bidirectional pin) | Pull-up on VCCRSTCLK_HPS voltage through a 1kΩ to 10kΩ resistor |
| SDMMC | Pull-up through 10kΩ resistor |
| Other |
When using QSPI larger than 128Mbit, it is necessary to use an IC with reset (Bootrom software operates in 3-byte mode, making it impossible to boot).
[Reference] CV SoC and AV Soc QSPI Boot (from RocketBoards.org) |
Dual-Use Pins
| Pin Name | Pin Name Comment |
|
CLKUSR DEV_OE DEV_CLRn PR_REQUEST |
Connect to GND when not used as each function pin and not used as user I/O pins |
| nPERST | Used as reset pin for PCIe hard IP |
I/O Pin (11)
When performing internal calibration, the RZQ pin needs to be processed.
Appendix: Cyclone® V MSEL Pin List
MSEL Pin Settings (FPGA Configuration)
| Device Family | Configuration Mode | Compression | Design Security | VCCPGM(V) | POR Delay | MSEL[4:0] Cyclone® V |
| Cyclone® V | FPP x8 | Disabled | Disabled | 1.8/2.5/3.0/3.3 | Fast | 10100 |
| Standard | 11000 Standard | |||||
| Disabled | Enabled | 1.8/2.5/3.0/3.3 | Fast | 10101 | ||
| Standard | 11001 Standard | |||||
| Enabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | 10110 | ||
| Standard | 11010 Standard | |||||
| FPP x16 | Disabled | Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard | |
| Standard | 00100 Standard | |||||
| Disabled | Enabled 1.8/2.5/3.0/3.3 | 1.8/2.5/3.0/3.3 | Fast | 00001 | ||
| Standard | Enabled | |||||
| Enabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | 00010 | ||
| Standard | 00110 Standard | |||||
| PS | Enabled/Disabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard | |
| Standard | 10001 Standard | |||||
| AS(x1, x4) | Enabled/Disabled | Enabled/Disabled | 3.0/3.3 | Fast | 10010 | |
| Standard | 10011 Standard |
MSEL Pin Settings (HPS Configuration)
| Device Family | Configuration Mode | Compression | Design Security | POR Delay | MSEL[4:0] (1) | cfgwdth | cdrratio | Partial Reconfiguration |
| Cyclone® V SoC via HPS | FPP x16 | Disabled Cfgwdth |
AES AES x16 Disabled |
Fast | 00000 | 0 | 1 | Standard |
| Standard | Standard | Standard 00100 | Standard 00100 0 | Standard 00100 0 1 | ||||
| Disabled |
AES Enabled |
Fast | 00001 | 0 | 2 | Standard | ||
| Standard | Standard | Standard 00101 | Standard 00101 0 | Enabled | ||||
| Enabled | Optional | Optional | 0 | 0 | 4 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ | Standard | ||
| Standard | Standard | Standard 00110 | Standard 00110 0 | Standard 00110 0 4 | ||||
| FPP x32 | Disabled |
AES AES Disabled |
Fast | 01000 | 1 | 1 | ×Standard | |
| Standard | 01100 | 1 x Standard 01100 | 1 | ×1 1 | ||||
| Disabled |
AES Enabled |
Fast | 01001 | Fast 01001 | 4 | ×Standard | ||
| Standard | 01101 | 1 x Standard 01101 | 4 × Standard 01101 1 | ×Enabled | ||||
| Enabled | Optional | Optional | 01010 | 1 | 8 x | ×Standard | ||
| Standard | 01110 | 1 x Standard 01110 | 8 × Standard 01110 | ×Standard 01110 1 8 |
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