Hello, my name is Masuo.
I am writing a series of articles on "Timing Analysis." The most difficult part of the training for newcomers was the lecture on timing analysis. In this column, I would like to summarize the lecture materials and notes on timing analysis, and introduce some of the stumbling blocks and useful information.
What Causes Timing Errors?
"We created a module with RAM and a multiplier for data a [8 bits] × data b [8 bits] = q [16 bits] (Figure 1)."
Figure 1: Module of multiplier and RAM
We want to operate at an operating frequency of 165.5 MHz. We have given the timing constraints in the SDC file as follows
====================== SDC file ===============================
/*constraint to 165.5MHz operating frequency*/
create_clock - period 6.042296073 - name clk1 [ get_ports { clk1 } ]
/*constraint the maximum and minimum input signal delay values*/
set_input_delay - clock { clk1 } - max 4.45 [ get_ports { data* } ] /* data synchronized to clk1 is input to FPGA with max 4.45ns delay*/
set_input_delay - clock { clk1 } - min 1.75 [ get_ports { data* } ] /* data synchronized to clk1 is input to FPGA with a minimum delay of 1.75ns*/
set_input_delay - clock { clk1 } - max 2.5 [ get_ports { rdaddress* wraddress* } ]
set_input_delay - clock { clk1 } - min 1.0 [ get_ports { rdaddress* wraddress* } ]
set_input_delay - clock { clk1 } - max 2.5 [ get_ports { wren } ]
set_input_delay - clock { clk1 } - min 1.0 [ get_ports { wren } ]
/*constraints on max/min delay values for output signals*/
set_output_delay - clock { clk1 } - max 0.7 [ get_ports { q* } ]
set_output_delay - clock { clk1 } - min 0.0 [ get_ports { q* } ]
==================================================================
After running the compilation and checking the timing report, we found a timing error (Figure 2). A closer look revealed that datab had a setup violation. In other words, the databases were arriving late relative to the receive edge. Ideally, we would like to operate at 165.5 MHz, but in reality, the maximum operating frequency was 164.72 MHz.
Figure 2: Timing Report
A closer look at the cause of the timing error reveals that it was due to "too long datapaths" in the multiplier module (Figure 3).
Figure 3. Detailed datapath arrival time report
As a solution, the following can be considered:
1. Shortening the wiring delay (IC: Interconnect).
2. Reducing the number of logic cells (CELL) between registers.
This column introduces the method of "1. shorten routing delay (IC)"!
Compile Options for Optimized Performance
Intel® Quartus® Prime development software offers compile options to optimize performance. This allows you to reduce IC delay by optimizing placement and routing.
Click Assignments menu > Settings > Fitter Settings > More Settings.... Set the Router Timing Optimization Level to "Maximum" (Figure 4).
The Router Timing Optimization Level, as the option name suggests, specifies the degree to which the routing is optimized to satisfy the timing constraints. Setting it to "Maximum" maximizes wiring optimization. (It is not guaranteed that all timing constraints can be satisfied by setting this option.)
Figure 4: Router Timing Optimization Level setting
Next, click on Assignments menu > Settings > Analysis & Synthesis. You can set the Optimization Technique field to 'Speed' (Figure 5)."
Selecting "Speed" will make the logic synthesis more focused on speed.
Figure 5.
After making the above two settings, we compiled again.
Figure 6. Optimized Compilation Report Result
Using the performance-optimized compilation option, the maximum operating frequency was 166.75 MHz, meeting the desired frequency of 165.5 MHz.
Conclusion
Performance-optimized compile options enable placement and routing with shorter IC delay.
In the next issue, we will show how to meet timing requirements by "2. reducing the number of logic cells (CELL) between registers."
New Engineer's Blush Blog Article List