Introduction
Hello, this is Tophu.
This issue is a continuation of the previous issue (Relationship between Quartus® Prime and Board Simulation - Derivation of IBIS File (1)).
In the previous article, we have completed creating the topology for simulation and assigning the model, so now it is time to run the simulation.
Running the Simulation
Open the previously created topology in HyperLynx® and launch Run Interactive Simulation and Show Waveforms.
The Digital Oscilloscope window will be launched.
Figure 1: Launch SI Simulation Tool (Run Interactive Simulation and Show Waveforms)
Figure 2: Digital Oscilloscope Screen
The Digital Oscilloscope displays the results of the IBIS simulation as a waveform.
In this example, we will simulate the case where a 200 MHz signal is output from the driver by the Oscillator. The settings are as shown below (Figure 3).
Click "Start Simulation" to start the simulation.
Figure 3: Simulation Settings (200 MHz signal output from the driver)
When the simulation is complete, waveforms are displayed as shown in Figure 3.
Figure 4: Simulation Result Waveform
Two waveforms are displayed, red is the driver waveform and yellow-green is the receiver waveform.
If we focus on the receiver (green) waveform, we can see that the waveform is greatly disturbed.
These are due to signal reflections in the transmission path.
If you want to know the cause of signal distortion, please read this article!
In this simulation, we used a very simple topology with just a driver and receiver connected.
In reality, as shown in Figure 5, we will create a topology on the board on Schematic, simulate it, and check the waveforms.
By conducting simulations before creating the board, the effects of transmission line length and wiring width can be checked and reflected in the board design, thus establishing a design flow with minimal rework.
Figure 5: Simulation of actual topology (example DDR3 clock lines)
In this article, we introduced how to simulate IBIS files generated by Quartus® Prime .
Various verifications are possible with HyperLynx. We will show you more in the future. Please look forward to it.
One last point
IBIS models can also be obtained from the website.
Let's compare the model selection screen of the file obtained from the web and the one generated by Quartus® Prime . The one on the left is the one generated by Quartus® Prime and the one on the right is the one obtained from the Web (Figure 6).
Figure 6: IBIS generated by Quartus® Prime on the left and IBIS downloaded from the Web on the right
Note the Signal part.
On the right are similar names such as 12_crnio_d2s0 and 12_crnio_d2s1. These are all the models for the pin configuration combinations that can be selected for the IO of a Cyclone® V device. In the case of Cyclone V, there are over 3000 configuration combinations, so choosing a model for your pin configuration can be a daunting task.
On the other hand, ibis generated from a Quartus® Prime project can generate an IBIS file that reflects the settings and names of each pin. This makes it easy to select models!
< Check also! > Quartus® Prime and Board Simulation
click here!
Relationship between Quartus® Prime and board simulation - Derivation of IBIS file (1)
Board Verification Tool HyperLynx