Hello, this is Masuo.
In my last column, I confirmed that the JTAG wiring was done correctly with "Auto Detect" and that the device was activated.
However, I found that my board was very unstable, sometimes the configuration succeeded, sometimes it failed.
I monitored the configuration errors.
The following table is taken from Hachi-Senpai's column " Configuration Sequence ".
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Signal name
|
Attribute
|
Value
|
Description
|
|
nCONFIG
|
Input
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High
|
Start configuration
|
|
Low
|
FPGA in reset state (POR in progress)
|
||
|
nSTATUS
|
Bidirectional open drain
|
Output = High
|
Normal configuration state
|
|
Output = Low
|
Configuration error
|
||
|
Input = High
|
Normal configuration state
|
||
|
Input = Low
|
Error state
|
||
|
CONF_DONE
|
Bidirectional open drain
|
Output = High (released)
|
Configuration data received complete
|
|
Output = Low
|
Before and during configuration
|
nCONFIG, nSTATUS, and CONF_DONE were observed on the oscilloscope (Figure 1).
Figure 1: Sequence of configuration failure (right figure shows enlarged red circled area)
- When nCONFIG goes High, configuration starts.
- nSTATUS is a signal to monitor configuration.
Figure 1 shows that the configuration keeps repeating Low (failure) and High (re-execution), indicating that the configuration keeps failing.
- CONF_DONE goes High when the configuration data reception is completed.
Figure 1 shows that it always remains low and the configuration is never completed.
Power and GND wiring are the main arteries of the board.
Senior "The GND wiring to the FPGA is a thin wire."
Masuo "It's a thin wire, but it's connected to GND properly, right?"
Senior "If the current capacitance of the power and GND wiring is small, the entire board will not operate properly because not enough current can flow. The power and GND wiring is the main artery of the board."
This is a view of the wiring on the back of the mass man's board ( Figure 2 ).
The GND wiring connected to the FPGA was a thin wire ( blue ), and the GND was designed to be very weak.
Figure 2: Weak GND
We strengthened the GND by using a wire twice as thick to increase the current capacitance ( Figure 3 ).
Figure 3: After GND reinforcement
With GND strengthened, configuration always succeeded and board operation became stable.
Figure 4 shows the configuration sequence measured with an oscilloscope after GND reinforcement.
Figure 4: Configuration Success Sequence
Figure 4 shows that the CONF_DONE pin went High because the configuration data reception was completed.
Senior "Did you design it considering the amount of current required for the entire board?"
Masuo "I considered the absolute maximum rating of the FPGA for the voltage, but I didn't think about the current."
Senior "It's a bad design not to consider the current. There is no way the board will work."
What I learned
Power and GND wiring is the main artery of the board.
We must design power and GND wiring that can supply the necessary current to the entire board.
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