Introduction.
Long time no see, my name is Tophu and I was in charge of the "blush blog" in fiscal year 2015.
I'm now a third-year employee, working hard in support.
I would like to introduce HyperLynx®, a tool that I have been using for a while now. Let's get started.
I came across the IBIS model generation YouTube video one day through the Intel® PSG (formerly Altera) newsletter (Monthly News Update).
＜IBIS model generation＞
https://www.youtube.com/watch?v=izcVsZGu2Ws
This video shows how to generate an IBIS file in Quartus® II (Quartus Prime), and when I followed the instructions, it did indeed generate an IBIS file.
However, there is no further introduction! I was puzzled as to how to use it, so I asked a senior colleague, and he replied, "HyperLynx! I asked a senior colleague how to use it, and he answered, "HyperLynx! So I actually tried it.
I created an IBIS file.
First, I created an IBIS file with Quartus. In the video, I used Quartus II, but of course I used Quartus Prime ver 16.1, which I am currently using.
Select Cyclone® V as device, turn on the setting to generate IBIS file, and run full compilation. This time, we used the DDR3 controller IP Example Design.
Figure 1: Quartus Prime Settings for IBIS file generation
After the full compilation is finished, I looked at the project folder and found that the board folder was created.
And in this folder, there is a file named ddr3_ctrl_01_example.ibs. This is the IBIS file. The file name is generated with the name of the project.
Now that we have the IBIS file, we can finally start using HyperLynx, which is already installed.
But first...
What is HyperLynx?
HyperLynx is a board verification tool from MentorGraphics. It can perform signal quality and power plane analysis of transmission lines on printed circuit boards. It allows for early detection of problems in board design.
⇒Board verification tool/HyperLynx - Siemens -Macnica
HyperLynx Startup
Start HyperLynx SI/PI. (HyperLynx series has more than SI/PI, but we will introduce them another time.
When you start HyperLynx, a screen similar to the one shown below (Figure 2) will appear. Click on "New SI Schematic".
Figure 2: After HyperLynx starts up, select the sheet you want to use (Schematic / Board / SI / PI, etc.)
Then a blank sheet is launched (Figure 3).
Figure 3: Launching the Schematic sheet for SI
This is the sheet used for LineSim in HyperLynx SI, also known as pre-simulation or pre-analysis, which creates the topology of the transmission lines between devices on the sheet for transmission line simulation.
This pre-simulation is an analysis before determining the layout and routing of the board and can be used to check the validity of the topology.
Creating the Topology
Let's create the topology on the sheet.
Oops, before we do that, we should originally set up the layer structure of the substrate. For this sample, we will use the default settings.
Incidentally, the layer configuration is set from the Stackup Editor. The default setting is a 6-layer board as shown below (Figure 4).
Figure 4: The layer configuration of the board can be changed in the Stackup Editor.
Close the Stackup Editor window and create the topology.
Let's simulate the address signal transmission path between Cyclone V and DDR3.
First, add a driver. The leftmost icon in the menu bar below at the top of the sheet is the IC pin.
Figure 5: Elements for Schematic (combine them to create a topology)
Click on this icon and click again at the desired location on the sheet to place the IC pins as shown below (Figure 6).
Figure 6: Placing driver pins
Next, add a transmission line. The transmission line is the fourth icon from the left. After placing the transmission line, connect it to the driver IC pin.
Finally, place another IC pin and connect it to the transmission line.
This completes the simplest topology (Figure 7).
Figure 7: Simple topology completed
Now, there is one more thing that must be done before simulation. That is the IC pin model assignment.
If you look closely at Figure 7, you will see that the driver and receiver IC pins are ???? and you can see that the IC pins for the driver and receiver are . This is because no IC pin model has been assigned.
Assigning IC Pin Models
Double-click the driver IC pin in Schematic.
Select the ddr3_ctrl_01_example.ibs created earlier, and the device model number 5CGXFC7.... In the Signal column, select the pin (model) you want to simulate. In this case, we want to simulate the address pin, so we select the mem_a[0] pin (Figure 8).
Figure 8: Selecting mem_a[0] pin from the IBIS model generated by Quartus
One point here:
You have selected mem_a[0], where mem_a is the name of the pin in the design. This is one advantage of generating IBIS files with Quartus.
More on this in the next issue.
Now that we have selected the pins (models) to be used for simulation from the IBIS models, the models are assigned to the IC pins in Schematic as shown in Figure 9.
Figure 9: IBIS model assignment to the driver is complete.
The receiver side is set up in the same way. Now we need to use the IBIS model of the DDR. This can be obtained from the memory vendor you are using, or you can download it from the Web.
Once the receiver model is set up, it should look like Figure 10. You are now ready to run the simulation.
Figure 10: IBIS model assignment completed for the receiver as well
We would like to run the simulation immediately, but that is all for this time.
In the next article, we will run the simulation. Enjoy the simulation!
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