Difference between VHDL and Verilog HDL ~ signals with different bit widths
Hello. My name is Ume Onigiri.
This time, I would like to introduce a stumbling block in HDL.
I designed the following circuit in VHDL for a training course.
The point of designing this circuit is the processing of the part circled in red in the figure. The description of this part is here.
If the input signals to the and circuit are 8 bits and 1 bit, Quartus® II's Analysis & Elaboration (HDL syntax check) will generate a syntax error.
It seems that VHDL does not allow signals with different bit widths to be input to the gate circuit.
Therefore, I converted the c signal to 8 bits by concatenating them.
By the way, the & is used for conjugation. In this case, since we want to use 8 bits
c & c & c & c & c & c & c & c & c & c
This time, since it is 8 bits, I used "&".
As a result, the error disappeared and the problem was solved.
I wondered if Verilog HDL also generates syntax errors when the bit width is different.
To make it easier to understand, I wrote the following circuit.
When I ran this circuit through Quartus II's Analysis & Elaboration, no error was found.
I found that the Verilog HDL specification allows signals with different bit widths to be input to the gate circuit.
But how does this process the signal?
Analysis shows that the upper 7 bits of the output are all processed as fixed 0s.
Even if we designed the first circuit with this, we would not be able to achieve the desired logic.
It was necessary to make a coupling connection here as well.
Incidentally, in Verilog HDL, if you use {8{b}} with duplication, the signal of b becomes 8 bits.
It was found that VHDL is designed to generate syntax errors when signals with different bit widths are input to the gate circuit.
On the other hand, Verilog HDL does not generate a syntax error even if the bit widths are different and processes the upper bit as 0.
Therefore, when designing the above circuit in Verilog HDL, the circuit will not function as desired even if no errors occur.
I learned this time that it is important to understand the specifications of each language, whether you design in Verilog HDL or VHDL. I learned that it is important to understand the specifications of both languages.
Recommended articles/documents are here
- Altera FPGA Development Flow / FPGA Top Page
- Verilog HDL
- Verilog HDL : Difference between Blocking and Non-blocking Logic Synthesis
- Difference between Verilog and VHDL - What I struggled with in conversion
- Difference between VHDL and Verilog HDL - signals with different bit widths
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