This problem has been resolved in Quartus Prime below. For details, please refer to the FAQ below.
Quartus® Prime Standard Edition Software v21.1 and later
Quartus® Prime Pro Edition Software v21.3 and later
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Hello.
My name is Altera Hanako and I am a technical support engineer for Altera® FPGA products at Macnica.
This is a must for users of EP4CE75 on Cyclone® IV !
Here is a workaround for a bug that occurs when writing jic files to the configuration ROM via FPGA.
Failure Status
The defect has been confirmed under the following conditions
| Tool |
Quartus® II 13.1.4 or later (including Quartus Prime Standard Edition and Lite Edition) |
| FPGA | EP4CE75 |
| File format to be transferred | .jic |
| Execution details |
Execute the Program option using the factory Enhanced SFL image to transfer the jic file to the configuration ROM.
<Programmer GUI image |
| Error messages generated by the Programmer | Error (209025) Can't recognize silicon ID for device ... |
Failure Cause
There is a bug in the Enhanced Serial Flash Loader (hereafter referred to as Enhanced SFL) image for the EP4CE75 in the Programmer for Quartus II 13.1.4 and later and Quartus Prime.
This bug has not been fixed in ver. 20.1 of Quartus Prime Standard and Lite Editions.
Workaround
Create your own SFL IP for EP4CE75 and transfer the jic file to the configuration ROM with the sof file.
The work procedure is as follows
- Create SFL IP
- Implement SFL IP in the top design
- Add timing constraints for your own SFL IP
- Compile
- Download sof file to EP4CE75
- Download the jic file
Now let us guide you through this work.
1. create SFL IP
In Quartus Prime, create a new workaround project and select EP4CE75 as the target device.
In the Tools menu > IP Catalog, select "Serial Flash Loader IP.
(If you are creating with Quartus Prime ver. 17.1 or earlier, the IP name is Altera Serial Flash Loader IP)
IP Catalog
Specify an arbitrary name for the IP and the folder to be created, and enable the following options on the General tab
Use enhanced mode SFL = On
Serial Flash Loader IP
[Click the "Generate HDL" button and specify the language to be generated.
Select Language
[Click the Generate button to generate the SFL IP.
Back to the top of the page 2.
2. implement SFL IP in the top design
Open a blank design file from File menu > New and create a top level design.
The entity name is arbitrary.
Implement the SFL IP created in step 1 in the top-level design.
(It is convenient to use the template for the instance in the folder where the IP was generated.)
To enable the SFL IP, connect the input noe_in port to GND.
The following is a VHDL design example.
Design Example (VHDL)
Select Assignments menu > Device > Device and Pin Options > Unused Pins, and click
Unused user I/O pins are set as follows.
Reserved all unused pins: As input tri-stated with weak pull-up
Reserved all unused pins
3. add timing constraints for your own SFL IP
Create a timing constraint file (.sdc) for the SFL IP.
Refer to the constraints published in the Knowledge Base of the manufacturer's web page.
## Example
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_generated_clock -name {ALTERA_DCLK} -source [get_ports {altera_reserved_tck}] -master_clock {altera_reserved_tck} }
[get_ports {*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
##
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 20.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 20.000 [get_ports {altera_reserved_tms}]]
set_input_delay -add_delay -clock [get_clocks {ALTERA_DCLK}] 11.000 [get_ports \}
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0}]
##
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 20.000 [get_ports {altera_reserved_tdo}]
set_output_delay -add_delay -max -clock [get_clocks {ALTERA_DCLK}] 0.000 [get_ports \}
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {ALTERA_DCLK}] 0.000 [get_ports \}
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}]
set_output_delay -add_delay -clock [get_clocks {ALTERA_DCLK}] 13.000 [get_ports \}
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SCE}]
set_output_delay -add_delay -clock [get_clocks {ALTERA_DCLK}] 8.000 [get_ports \}
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_SDO}]
##
remove_clock_groups -all
##
set_false_path -from [get_ports {altera_reserved_tck}] -through [get_nets \
{*altserial_flash_loader_component|\ENHANCED_PGM:sfl_inst_enhanced|dclkin~0}] -to [get_keepers \
{*altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DCLK}][Note] The ending number of \GEN_ASMI_TYPE_1 may be different.
After creating and saving the sdc file, register the .sdc file to the project using the following menu.
Assignments menu > Settings > Timing Analyzer category
4. compile
Execute compilation.
Processing menu > Start Compilation
Download sof file to EP4CE75
Start the Programmer (Tools menu > Programmer). (Tools menu > Programmer)
Set Hardware Setup and select JTAG for Mode.
Set the sof file generated by compilation and enable (On) the Program/Configure option.
Programmer (set .sof for SFL)
[Click the "Start" button to transfer data to the EP4CE75.
After writing is complete, delete the sof file from the Programmer's screen by clicking the [Delete] button.
6. download jic file
Register the jic file created in advance in the Programmer.
Enable (On) the Program/Configure option of the jic file.
Programmer (.jic file is set)
[Reference: jic file creation]
Quartus® Guide - Generating and Converting Programming Files
Programming to EPCQ devices via FPGA (JIC programming)
Disable (Off) the Factory default enhanced SFL image Program/Configure option only.
The SFL image has already been downloaded to the EP4CE75 according to step 5.
Programmer (transfer jic files only)
[Click the "Start" button to download the jic file only.
This completes the operation.
Please use this method to avoid writing the jic file to the configuration ROM via the EP4CE75.
Click here for recommended articles/documents
Altera® FPGA Development Flow / FPGA Top Page
Quartus® Guide - Generating and Converting Programming Files (Convert Programming Files)
Programming to EPCQ Devices via FPGA (JIC Programming)