Nice to meet you, my name is Topu.
I joined the company in April 2015 and am the new blogger.
Please take care of me!
This time I would like to discuss how to define I/O timing relationship between external devices and FPGA.
We were taught about timing analysis* in the training.
We did an exercise to define input/output delays in the description of an SDC file.
In this exercise, we defined the timing of input pins with respect to signals coming from external devices.
Figure 1: Relationship between external device and FPGA
clk_in_100 mhz_vir is defined by the following expression.
create_clock - name clk_in_100 mhz_vir - period 10.000
When defining the delay of an external signal on the 8-bit din_a [7:0] pins, we need to constrain the input setup time and input hold time.
There are three types of delays associated with data coming from external devices:
1. internal register delay, 2. on-board delay, and 3. clock skew on the board.
In this exercise, we will use the delay times defined in the table below.
|
Minimum |
Maximum |
|
|
Delay inside register tco (ns)
|
1 |
3 |
|
On-board delay (device-to-device) (ns)
|
0.5 |
0.5 1 |
|
Board clock skew (ns)
|
-0.5 |
0.5 |
Table 1. Delay Times
Use the above table to place constraints on external data inputs for all input data pins.
Here is how to describe it
set_input_delay-clock {clock to drive external registers} - max max max input delay[ get_ports {input pin name}]
set_input_delay-clock {clock to drive external registers} - min min min input delay[ get_ports {input pin name }]
These two values maximum input delay and minimum input delay are obtained by the following equations.
Maximum input delay = board delay ( max ) - clock skew ( min ) + tco ( max )
Minimum input delay = board delay ( min ) - clock skew ( max ) + tco ( min )
(The maximum input delay constrains the setup time and the minimum input delay constrains the hold time.)
In the example in this exercise, the following two lines should be written for din_a[0].
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[0]}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [get_ports {din_a[ 0]}]
If you write all of this from din_a[0] ~ din_a[7], you get the following.
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[0]}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [get_ports {din_a[ 0]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[1]}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [get_ports { din_a[1]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[2]}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [get_ ports {din_a[2]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[3]}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [ get_ports {din_a[3]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[4]}]
set_input_delay -clock {clk_in_100mhz_vir } - min 1 [get_ports {din_a[4]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[5]}]
set_input_delay -clock {clk_in_100mhz_ vir } -min 1 [get_ports {din_a[5]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[6]}]
set_input_delay -clock {clk_in_100 mhz_vir } -min 1 [get_ports {din_a[6]}]
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a[7]}]
set_input_delay -clock {clk_in _100mhz_vir } -min 1 [get_ports {din_a[7]}]
Now the input pin constraints from the external signals are perfect!
However, if we were to use the above as a constraint not only for the din_a pin, but for all other pins, it would be a bit cumbersome & not smart to write.
(I've written 16 lines of almost the same content at ・・・・)
I was wondering if there was a cleaner and quicker way to describe it, and my senior instructor told me that there is a way to do it with only 2 lines! I was wondering if there was a cleaner and quicker way to write the code.
Here it is.
set_input_delay -clock {clk_in_100mhz_vir } -max 4.5 [get_ports {din_a*}]
set_input_delay -clock {clk_in_100mhz_vir } -min 1 [get_ports {din_a*}]
By adding an * (asterisk) after the -a, the same description can be used for whatever is written under din_a.
In other words, the previous 16 lines can be written in two lines.
This "*" is called a wildcard, and allows you to write SDC files without much trouble.
Wildcards are apparently commonly used in information processing (Linux, C language, etc.).
(I didn't know about wildcards, so I was impressed when I learned about them at the training. )
This wildcard can be used in SDC files, so there is no way to avoid using it!
Summary
- There are three elements of delay in setting input pins, all of which must be taken into account in the description.
- Using the wildcard can reduce the description across multiple lines. → cleaner description + time savings
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