When creating a board to implement an Altera FPGA, designers use the documentation published by the manufacturer as a reference to create a schematic.
This section focuses on points of particular concern.
Altera Quartus® Prime development software (hereafter referred to as Quartus Prime) can also be used to verify placement based on the various constraints of the device.
Please use Quartus Prime in addition to the schematic check in the document.
Target FPGAs
Arria® V FPGAs (excluding Arria V GZ)
Preparation
Here are some documents that you can refer to when creating your schematics.
| Pin Connection Guidelines | Schematic Review Worksheet |
| Arria® V GT, GX, ST, and SX Device Family Pin Connection Guidelines | Arria® V GX, GT, SX, and ST Device Schematic Review Worksheet |
Arria V Overview (FPGA TOP)
The figure below shows the pins that require special attention when designing the Arria V board.
The placement of the pins in the figure has nothing to do with the actual device.
Click each item to see the check points.
VCC, VCC for HPS, VCC for transceiver
| Apply the recommended power supply voltage by referring to the datasheet. |
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● Provide a measurement point near the FPGA. ● Provide a measurement point near the FPGA ● Make sure that the power supply can be measured in case of a failure |
| Refer to the Power & Thermal Design & Debug Guidelines |
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If all GXBs (transceivers) on the same side are not in use, use the following VCCR_GXB[L,R], VCCT_GXB[L,R], VCCL_GXB[L,R], VCCH_GXB[L,R], and VCCA_GXB[L,R] can be connected to GND |
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Number of decoupling capacitors Estimate the number of decoupling capacitors by referring to the PDN tool. For more detailed estimation, use a dedicated tool. <Reference Power supply network (PDN) analysis tool Part 9 Confirmation and Review of Capacitance in FPGA Power Supply Design |
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When configuring in Active Serial (AS) mode When configuring in Active Serial (AS) mode, VCCPGM should be 3.0 V or 3.3 V. |
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Power Supply Sequence
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MSEL Pins
For MSEL pin information on Arria V, please refer to the following.
| MSEL Pin Settings | Insert pull-up/pulldown resistors (1)(2) |
| Arria V |
Not required ( see this document ) |
| Arria® V SoC via HPS |
(1) Weak Pull-Down Resistor (25kΩ) is inserted inside.
(2) If you want to switch the configuration mode, switch to VCCPGM/GND with a 0Ω resistor.
For a list of MSEL pins, click here.
Configuration pins
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DCLK Damping resistor insertion is recommended (minimum 0Ω) 10-50Ω In AS mode, take care of trace length (see document below) |
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nCONFIG, nSTATUS Pull-up to VCCPGM via 10kΩ resistor |
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CONF_DONE Pulled up to VCCPGM via 10kΩ resistor Do not connect to LED as it is. - Do not connect to LED as it is ● Due to insufficient drive current, LED may not light up unless FET is applied. |
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If FPGAs are cascaded, pull up nSTATUS and CONF_DONE in common. INIT_DONE is pulled up individually (only if used) |
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nCE GND connection or pull-down through 10kΩ resistor This signal determines whether the FPGA is cascaded or not. |
| When nCEO is used, pull-up to VCCPGM via 10kΩ resistor |
JTAG pin
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Check Point Insertion of a damping resistor with 0Ω resistance is recommended for TCK. - To enable handling of cases where writing cannot be performed due to clock system trouble. |
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To enable handling of cases in which write cannot be performed due to clock system trouble. TCK: Pulled down via 1kΩ resistor (Pulled down via 1kΩ resistor even when not used) TDI : Pull-up to VCCPD via 1kΩ to 10kΩ resistor (When not used, pull-up via 1kΩ resistor) TMS : Pull-up to VCCPD through 1kΩ to 10kΩ resistor (Pull-up through 1kΩ resistor when not used) TDO : No pull-up/pulldown (Open when not used) |
| When cascading three or more FPGAs, insert buffers on the TCK and TMS lines. |
Clock Input Pin (5)
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When using single-ended clock, assign to p-channel. (The n channel does not directly ride on the global clock, which limits the use of the ALTCLKCTRL buffer.) |
| Note AC/DC coupling when using differential inputs. |
Other Dedicated Pins
| Pin name | Pin Name Comment |
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RREF_TL RREF_BR |
Pull-down through 2kΩ resistor when using PLL (resistor accuracy ±1%) |
| VREF | Connect to VCCIO or GND if not used as a dedicated pin |
Transceiver pin
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If the transceiver is not used, connect to GND. Clock (REFCLK_*) is connected to GND RX (GXB_RX_*, GXB_REFCLK_*) is connected to GND TX (GXB_TX_*) is floating. |
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AC/DC coupling AC/DC coupling |
DDR3 pin
Check the following guidelines by referring to the following web contents.
Arria® V / Cyclone V and DDR3 schematic check items (from Ultima Company's technical contents)
Pins that are especially easy to mistake
- mem_reset_n
- mem_cke
- rzq
HPS pins
| Arria V SoC Pin name | CLOCKSEL[1:0] CLOCKSEL[1:0 |
| CLOCKSEL[1:0] (1:0) | Pulls up or down on VCCIO voltage through 4.7kΩ to 10kΩ resistors |
| BOOTSEL[2:0] | Pull-up or pull-down across a 4.7kΩ to 10kΩ resistor to VCCIO voltage |
| HPS_nRST (bidirectional pin) | Pull-up across a 1kΩ to 10kΩ resistor to VCCRSTCLK_HPS voltage |
| SDMMC | Pull-up across 10kΩ resistor |
| Other |
When using QSPI larger than 128Mbit, it is necessary to use an IC with reset (Bootrom software operates in 3-byte mode, making it impossible to boot).
[Reference] CV SoC and AV Soc QSPI Boot (from RocketBoards.org) |
Dual-Use Pins
| Pin Name | Pin Name Comment |
| CLKUSR |
If this pin is not used as a function pin and is not used as a user I/O pin, set Reserved Pin = "As output driving ground" in Quartus Prime and connect to GND. Set Reserved Pin = "As output driving ground" in Quartus Prime and connect to GND. |
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DEV_OE DEV_CLRn PR_REQUEST |
If these pins are not used as function pins and are not used as user I/O pins, connect to GND. |
| nPERST | Used as reset pin for PCIe hard IP |
I/O Pin (11)
When performing internal calibration, the RREF_TL / RREF_BR pins need to be processed.
Appendix : Arria V MSEL Pin List
MSEL Pin Settings (FPGA Configuration)
| Device Family | Configuration Mode | Compression | Design Security | VCCPGM(V) | POR Delay | MSEL[4:0] Arria V |
|
Arria V (except Arria V GZ) |
FPP x8 | Disabled | Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard |
| Standard | 11000 Standard | |||||
| Disabled | Enabled | 1.8/2.5/3.0/3.3 | Fast | 10101 | ||
| Standard | 11001 Standard | |||||
| Enabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | 10110 | ||
| Standard | 11010 Standard | |||||
| FPP x16 | Disabled | Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard | |
| Standard | 00100 Standard | |||||
| Disabled | Enabled 1.8/2.5/3.0/3.3 | 1.8/2.5/3.0/3.3 | Fast | 00001 | ||
| Standard | Enabled | |||||
| Enabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard | ||
| Standard | 00110 Standard | |||||
| PS | Enabled/Disabled | Enabled/Disabled | 1.8/2.5/3.0/3.3 | Fast | Standard | |
| Standard | 10001 Standard | |||||
| AS(x1, x4) | Enabled/Disabled | Enabled/Disabled | 3.0/3.3 | Fast | 10010 | |
| Standard | 10011 Standard |
MSEL Pin Settings (HPS Configuration)
| Device Family | Configuration Mode | Compression | Design Security | POR Delay | MSEL[4:0] (1) | cfgwdth | cdrratio | Partial Reconfiguration |
| Arria V SoC via HPS | FPP x16 | Disabled |
AES AES Disabled |
Fast | 00000 | 0 | 1 | Standard |
| Standard | Standard | Standard 00100 | Standard 00100 0 | Standard 00100 0 1 | ||||
| Disabled |
AES Enabled |
Fast | 00001 | 0 | 2 | Standard | ||
| Standard | Standard | Standard 00101 | Standard 00101 0 | Enabled | ||||
| Enabled | Optional | Optional | 0 | Optional Fast 00010 | Optional Fast 00010 0 | Standard | ||
| Standard | Standard | Standard 00110 | Standard 00110 0 | Standard 00110 0 4 | ||||
| FPP x32 | Disabled |
AES AES Disabled |
Fast | 01000 | 1 | 1 | ×Standard | |
| Standard | 01100 | 1 x Standard 01100 | 1 | ×1 1 | ||||
| Disabled |
AES Enabled |
Fast | 01001 | Fast 01001 | 4 | ×Standard | ||
| Standard | 01101 | 1 x Standard 01101 | 4 × Standard 01101 1 | ×Enabled | ||||
| Enabled | Optional | Optional | 01010 | 1 | 8 x | ×Standard | ||
| Standard | 01110 | 1 x Standard 01110 | 8 × Standard 01110 | ×Standard 01110 1 8 |
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