This series of "Quartus® Beginner's Guide" is intended for users who are new to Quartus® Prime / Quartus® II development software.
FPGA / CPLD Development Flow For more information on the FPGA / CPLD development flow, click HERE for more information on the FPGA / CPLD development flow.
Description
This document will help you during the "5. Setting Constraints" phase of FPGA / CPLD development.
It describes how to place timing constraints on the target FPGA / CPLD design (circuit) in Quartus® Prime / Quartus® II development software.
This document describes how to create a timing constraint file (SDC file) that is used to place timing constraints on an FPGA / CPLD design (circuit). Synopsys Design Constraints (SDC) files, originally a standard format in the ASIC industry, can be used for timing constraints in FPGAs and CPLDs, and can be referenced as a target (guide) in the Quartus® Prime / Quartus® II development software Fitter (Place and Route). The SDC files are not only referenced as targets (guides) in the Quartus® Prime / Quartus® II development software, but are also used for high-performance timing analysis by the TimeQuest Timing Analyzer.
Recommended Articles
Quartus® Getting Started Guide - How to Perform Timing Analysis
Altera® FPGA Development Flow / FPGA Home Page
Documentation
quartus-hg_timing-constraint_v1710_r2__1.pdf: "Quartus® Prime Beginner's Guide - How to Constrain Timing with TimeQuest ver.17" (Rev.2 document for tool version: Ver.17.1)
quartus-hg_timing-constraint_v1500_r2__1.pdf: "Quartus II Getting Started Guide - Timing Constraints with TimeQuest ver.15" (Rev.2 document for tool version: Ver.15.0)