Hello, my name is Masuo.
Starting this week, I will be writing a series of articles on "timing analysis."
The most difficult part of the training for newcomers was the lecture on timing analysis.
In this column, I would like to summarize the lecture materials and notes on timing analysis and introduce some points that I stumbled upon.
Today we will discuss SDC files.
What is timing analysis?
Timing analysis is to verify whether an FPGA operates correctly at a certain operating frequency.
For more details, please refer to Timing Analysis Series 1 "Concepts of Timing Analysis"
SDC file is required for timing analysis
One of the most difficult parts of the timing analysis training was the SDC (Synopsys Design Constraints) description.
What is a Synopsys Design Constraints file?
SDC file is a standard format for timing constraints in the ASIC industry and has been adopted by the FPGA industry.
An SDC file is required for timing analysis. First, we will show you how to create a new SDC file. 1.
1. compile your design and launch TimeQuest Timing Analyzer
Quartus® II screen
2. create a Netlist
Click Netlist > Create Timing Netlist ...
TimeQuest Timing Analyzer screen
Click OK on Create Timing Netlist to complete Netlist generation.
Create Timing Netlist screen
Create SDC File
Click File > New SDC File.
Describe SDC constraints in text-based format.
SDC File Screen
What is described in an SDC file?
The following URL is an example of SDC description.
Example of SDC description in TimeQuest
To summarize briefly
Describe the operating frequency
Input/output I/O describes FPGA external timing such as board delay information.
By describing these two pieces of information in SDC, it is possible to analyze whether the FPGA operates without problems.
Quartus® II has information on "routing delay time" and "register output delay time" inside the FPGA.
However, "operating frequency" and "I/O delay information" external to the FPGA must be provided to Quartus II by the user, which is the SDC file!
SDC is easily written with TimeQuest Timing Analyzer
No need to learn SDC description language. (←No worries!)
You can write SDC easily with GUI of TimeQuest Timing Analyzer. 4.
Launch GUI for SDC commands
From the newly created SDC file, click Edit > Insert Constraint.
SDC file screen
5. SDC command description of operating frequency
The following is an example of a clock constraint description. Select Create Clock....
･Clock name : Enter any name.
･Period : Enter the operating frequency.
･Targets : Select the clock signal name defined in HDL.
Summary
･To perform timing analysis, SDC is required.
･SDC is a text file that describes external delay information for the device.
･SDC commands can be easily written using the GUI of the TimeQuest Timing Analyzer.
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