Hello, this is Masuo.
This is the last installment of the "Timing Analysis Series." The most difficult part of the newcomer training was the timing analysis lecture.
In this column, I would like to summarize the timing analysis lecture materials and notes, and introduce some of the stumbling blocks and useful information.
What Causes Timing Errors?
We designed a module for a multiplier and RAM operating at 165.5 MHz (Figure 1) and analyzed the timing, and found a timing error (Figure 2) in the databases.
Figure 1: Multiplier module
Figure 2: Timing Report
As a solution, the following can be considered:
1. Shortening the wiring delay (IC: Interconnect).
2. Reducing the number of logic cells (CELL) between registers.
This column introduces the method of "2. Reducing the number of logic cells (CELL) between registers!
Pipelining
The timing analysis tool TimeQuest analyzes the path between all transmit and receive registers. Therefore, data delays can be improved by reducing the number of logic cells between registers. Inserting registers between logic cells is called "pipelining" (Figure 3). *Inserting registers reduces the number of logic cells between registers, which improves timing but increases latency. In Figure 3 below, the increase in latency is 2 cycles, meaning that the result of the operation is output 2 cycles later.
Figure 3: Pipelining Image
The MegaWizard multiplier (LPM_MULT) provided by Intel has an optional pipelining setting (Figure 4). The setting was changed to Output latency of "4" clock cycles.
Figure 4. LPM_MULT parameter setting screen
When arithmetic operations (especially multiplication and division operations) are realized in hardware (FPGA), it is necessary to take into account that timing becomes more and more demanding. As the number of bits for arithmetic operations increases, the circuit scale increases in proportion to the Beki multiplier, and the number of logic cells between registers increases, resulting in tighter timing (Figure 5).
Figure 5: RTL Viewer of the Multiplier
By pipelining the multiplier, the maximum operating frequency was 168.75 MHz, meeting the desired frequency of 165.5 MHz.
Lessons Learned
Pipelining and subdividing logic cells can avoid timing errors. However, when pipelining, latency must be taken into account in the design.
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